ADP3000

–7–

REV. 0

Table II. Recommended Capacitors

Vendor

Series

Type

Phone Numbers

AVX

TPS

Surface Mount

(803) 448-9411

Sanyo

OS-CON

Through-Hole

(619) 661-6835

Sprague

595D

Surface Mount

(603) 224-1961

Panasonic

HFQ

Through-Hole

(201) 348-5200

DIODE SELECTION

The ADP3000’s high switching speed demands the use of

Schottky diodes. Suitable choices include the 1N5817, 1N5818,

1N5819, MBRS120LT3 and MBR0520LT1. Do not use fast

recovery diodes because their high forward drop lowers effi-

ciency. Neither general-purpose diodes nor small signal diodes

should be used.

PROGRAMMING THE SWITCHING CURRENT LIMIT

OF THE POWER SWITCH

current limit to be programmed with a single external resistor.

This feature offers major advantages which ultimately decrease

the component cost and P.C.B. real estate. First, it allows the

ADP3000 to use low value, low saturation current and physi-

cally small inductors. Additionally, it allows the ADP3000 to

use a physically small surface mount tantalum capacitor with a

typical ESR of 0.1

Ω to achieve an output ripple as low as 40

mV to 80 mV, as well as low input ripple.

As a rule of thumb, the current limit is usually set to approximately

3 to 5 times the full load current for boost applications and

about 1.5–3 times of the full load current in buck applications.

Q1 is the ADP3000’s internal power switch, which is paralleled

by sense transistor Q2. The relative sizes of Q1 and Q2 are

scaled so that IQ2 is 0.5% of IQ1. Current flows to Q2 through

both an internal 80

Ω resistor and the R

on these two resistors biases the base-emitter junction of the

oscillator-disable transistor, Q3. When the voltage across R1

pulse. If only the 80

Ω internal resistor is used (i.e. the I

be 1.5 A. Figure 8a gives values for lower current-limit values.

POWER

SWITCH

SW2

SW1

DRIVER

80

Ω

(INTERNAL)

200

(EXTERNAL)

Q2

ADP3000

Q1

400kHz

OSC

Q3

R1

Figure 17. ADP3000 Current Limit Operation

The delay through the current limiting circuit is approximately

0.3

µs. If the switch ON time is reduced to less than 1.7 µs,

accuracy of the current trip-point is reduced. Attempting to

program a switch ON time of 0.3

µs or less will produce

spurious responses in the switch ON time. However, the

ADP3000 will still provide a properly regulated output voltage.

PROGRAMMING THE GAIN BLOCK

The gain block of the ADP3000 can be used as a low battery

detector, error amplifier or linear post regulator. The gain block

consists of an op amp with PNP inputs and an open-collector

NPN output. The inverting input is internally connected to the

ADP3000’s 1.245 V reference, while the noninverting input is

available at the SET pin. The NPN output transistor will sink in

excess of 300

µA.

Figure 18 shows the gain block configured as a low battery

monitor. Resistors R1 and R2 should be set to high values to

reduce quiescent current, but not so high that bias current in

the SET input causes large errors. A value of 33 k

Ω for R2 is a

good compromise. The value for R1 is then calculated from the

formula:

R1

=

1.245 V

R2

gain block output is an open-collector NPN, a pull-up resistor

should be connected to the positive logic power supply.

ADP3000

1.245V

REF

GND

AO

5V

47k

Ω

TO

PROCESSOR

R1

SET

R2

33k

Ω

1.6M

Ω

R1 =

37.7µA

Figure 18. Setting the Low Battery Detector Trip Point