ADMC401 datasheet(38/60 Pages) AD

38 / 60 page

REV. B

ADMC401

–38–

asynchronous timing of encoder and DSP-reading events. As a

result, more accurate computations of the position and velocity

of the motor shaft may be performed.

The EET consists of a 16-bit encoder event timer, an encoder

pulse decimator and a clock divider. The EET clock frequency is

selected by the 16-bit read/write EETDIV clock divide register,

whose value divides the CLKOUT frequency. The contents of

the encoder event timer are incremented on each rising edge of

the divided clock signal. An EETDIV value of zero gives the

maximum divide value of 0x10000 (= 65,536), so that the

clock frequency to the encoder event timer is at its minimum

possible value.

The quadrature signal from the encoder interface unit is deci-

mated at a rate determined by the 8-bit read/write EETN regis-

ter. For example, writing a value of two to EETN, produces a

pulse decimator output train at half the quadrature signal fre-

quency, as shown in Figure 31. The rising edge of this deci-

mated signal is termed a velocity event. Therefore, for an EETN

value of two, a velocity event occurs every two encoder edges, or

on each edge of one of the encoder signals. An EETN value of 0

gives an effective pulse decimation value of 256.

On the occurrence of a velocity event, the contents of the en-

coder event timer are stored in an intermediate Interval Time

time between successive velocity events. After the timer value

has been latched at the velocity event, the contents of the en-

coder event timer are reset to one.

ENCODER EVENT

TIMER VALUE

EET LATCH

EVENT

VELOCITY

EVENTS

QUADRATURE

SIGNAL

EIUCNT

EETT

EETDELTAT

Figure 31. Operation of Encoder Interface Unit and EET of

ADMC401 in the Forward Direction with EETN = 2

Latching Data from the EET

When using the data from the Encoder Event Timer, it is im-

portant to latch a triplet set of data at the same instant in time.

The three pieces of data are the contents of the encoder quadra-

ture up/down counter, the stored value in the Interval Time

velocity events) and the present value of the encoder event timer

(giving an indication of how much time has passed since the last

velocity event).

The data from the EET can be latched on the occurrence of

two different events. The particular event is selected by

Bit 4 (EETLATCH) of the EIUCTRL register. Setting this

EETLATCH bit causes the data to be latched on the timeout of

the encoder loop timer (EIUTIMER). At that time, the contents

of the encoder quadrature counter (EIUCNT) are latched to a

16-bit register EETCNT. In addition, the contents of the inter-

mediate Interval Time register are latched to the EETT register

and the contents of the encoder event timer are latched to the

EETDELTAT register. The three registers, EETCNT, EETT

and EETDELTAT, then contain the desired triplet of position/

speed data required for the control algorithm. In addition, if the

timeout of the EIUTIMER is used to generate an EIU loop

timer interrupt, the required data is automatically latched and

waiting for execution of the interrupt service routine (which may

be some time after the timeout instant if there are multiple

interrupts in the system). By latching the EIUCNT register to

the EETCNT, the user does not have to worry about changes in

the EIUCNT register (due to additional encoder edges) prior to

servicing of the EIU loop timer interrupt.

The other EET latch event is defined by clearing the EETLATCH

bit of the EIUCTRL register. In this mode, whenever, the

EIUCNT register is read by the DSP, the current value of the

intermediate Interval Time register is latched to the EETT

to the EETDELTAT register. The three registers, EIUCNT,

EETT and EETDELTAT now contain the desired triplet of

position/speed data required for the control algorithm. Note the

difference from before, in that the encoder count value is now

available in the EIUCNT register.

It is important to realize that the EETT, and EETDELTAT regis-

ters are only updated by either the timeout of the EIUTIMER

EIUCNT register (if the EETLATCH bit is cleared). Therefore,

if the EETLATCH bit is set, the act of reading the EIUCNT

Following reset, Bit 4 of the EIUCTRL is cleared.

EET Status Register

There is a 1-bit EETSTAT register that indicates whether or

not an overflow of the EET has occurred. If the time between

successive velocity events is sufficiently long, it is possible that

the encoder event timer will overflow. When this condition is

detected, Bit 0 of the EETSTAT register is set and the EETT

clears the overflow bit and permits the EETT register to be

updated at the next velocity event.

If an encoder direction reversal is detected by the EIU, the

encoder event timer is set to 1 and the EETT register is set to

its maximum 0xFFFF value. Subsequent velocity events will

cause the EETT register to be updated with the correct value. If

a value of 0xFFFF is read from the EETT register, Bit 0 of the

EETSTAT register can be read to determine whether an over-

flow or direction reversal condition exists.

On reset the EETN, EETDIV, EETDELTAT and EETT regis-

ters are all cleared to zero. Whenever either the EETN or EETDIV

registers are written to, the encoder event timer is reset to zero

and the EETT register is set to zero.

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