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ADMC328YN датащи(PDF) 16 Page - Analog Devices

номер детали ADMC328YN
подробное описание детали  28-Lead ROM-Based DSP Motor Controller with Current Sense
PDF  32 Pages
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ADMC328YN датащи(HTML) 16 Page - Analog Devices

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ADMC328
–16–
REV. B
The second method for detecting a fault condition is through
the ISENSE pin in the analog block of the ADMC328. The ISENSE
pin monitors the feedback signals from a dc bus current sensing
resistor that represents the total current in the motor. When the
voltage of ISENSE goes below ISENSE trip threshold, PWMTRIP
will be internally pulled low. The negative edge of the internal
PWMTRIP will generate a shutdown in the same manner as a
negative edge on pin PWMTRIP.
It is possible through software to initiate a PWM shutdown by
writing to the 1-bit read/write PWMSWT register (0x2061).
Writing to this bit generates a PWM shutdown in a manner
identical to the PWMTRIP or ISENSE pins. Following a PWM
shutdown, it is possible to determine if the shutdown was gener-
ated from hardware or software by reading the same PWMSWT
register. Reading this register also clears it.
Restarting the PWM after a fault condition is detected requires
clearing the fault and reinitializing the PWM. Clearing the fault
requires that PWMTRIP returns to a HI state and ISENSE returns
to a voltage greater than the ISENSE trip threshold. After the fault
has been cleared, the PWM can be restarted by writing to registers
PWMTM, PWMCHA, PWMCHB and PWMCHC. After the fault
is cleared and the PWM registers are initialized, internal timing
of the three-phase timing unit will resume, and the new duty cycle
values will be latched on the next rising edge of PWMSYNC.
PWM Registers
The configuration of the PWM registers is described at the end
of the data sheet. The parameters of the 16-bit PWM Timer is
tabulated in Table V.
ADC OVERVIEW
The ADC of the ADMC328 is based upon the single slope
conversion technique. This approach offers an inherently
monotonic conversion process and, to within the noise and sta-
bility of its components, there will be no missing codes.
Table VI. ADC Auxiliary Channel Selection
MODECTRL (1)
MODECTRL (0)
Select
ADCMUX1
ADCMUX0
VAUX0
0
0
VAUX1
0
1
VAUX2
1
0
Calibration (VREF)1
1
The single slope technique has been adapted on the ADMC328
for four channels that are simultaneously converted. Refer to
Figure 11 for the functional schematic of the ADC. Two of the
main inputs (V1 and V2) are directly connected as high imped-
ance voltage inputs. The third main input channel (ISENSE) has a
special design to monitor the voltage on a current-sensing resis-
tor whose voltage is always below (more negative than) GND. The
fourth channel has been configured with a serially-connected
4-to-1 multiplexer. Table VI shows the multiplexer input selection
codes. One of these auxiliary multiplexed channels is used to cali-
brate the ramp against the internal voltage reference (VREF).
VAUX0
V2L
VAUXL
PWMSYNC (CONVST)
ADC
REGISTERS
V1L
V3L
V2
ISENSE
(CAP RESET)
CLK MODECTRL<7>
12-BIT
ADC
TIMER
BLOCK
PWMTRIP
VREF
COMP
ADC REGISTERS
ADC1
ADC2
ADC3
ADCAUX
MODECTRL<0..1>
EXTERNAL
CHARGING
CAP
VC
ICONST
ICONST_TRIM<2:0>
VAUX1
VAUX2
COMP
COMP
COMP
V1
COMP
–5 X
0.8 X
C
GND
4 – 1
MUX
Figure 11. ADC Overview
Comparing each ADC input to a reference ramp voltage, and tim-
ing the comparison of the two signals, performs the conversion
process. The actual conversion point is the time point intersec-
tion of the input voltage and the ramp voltage (VC) as shown in
Figure 12. This time is converted to counts by the 12-bit ADC
Timer Block and is stored in the ADC registers. The ramp volt-
age used to perform the conversion is generated by driving a
fixed current into an off-chip capacitor, where the capacitor
voltage is
VC = (I/C) × t
Table V. Fundamental Characteristics of PWM Generation Unit of ADMC328
16-BIT PWM TIMER
Parameter
Min
Typ
Max
Unit
Counter Resolution
16
Bits
Edge Resolution (Single Update Mode)
100
ns
Edge Resolution (Double Update Mode)
50
ns
Programmable Dead Time Range
0
100
µs
Programmable Dead Time Increments
100
ns
Programmable Pulse Deletion Range
0
100
µs
Programmable Pulse Deletion Increments
100
ns
PWM Frequency Range
150
Hz
PWMSYNC Pulsewidth (TCRST)
0.05
12.5
µs
Gate Drive Chop Frequency Range
0.02
5
MHz



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