ADMC326 datasheet(19/31 Pages) AD

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ADMC326

–19–

REV. A

PWM DAC Equation

The auxiliary PWM output can be filtered in order to produce a

low frequency analog signal between 0 V to VDD. For example, a

2-pole filter with a 1.2 kHz cutoff frequency will sufficiently at-

tenuate the PWM carrier. Figure 17 shows how the filter would

be applied.

R1 = R2 = 13k

C1 = C2 = 10nF

AUXPWM

Figure 17. Auxiliary PWM Output Filter

WATCHDOG TIMER

The ADMC326 incorporates a watchdog timer that can perform

a full reset of the DSP and motor control peripherals in the

event of software error. The watchdog timer is enabled by writ-

ing a timeout value to the 16-bit WDTIMER register. The timeout

value represents the number of CLKIN cycles required for the

watchdog timer to count down to zero. When the watchdog timer

reaches zero, a full DSP core and motor control peripheral reset

is performed. In addition, Bit 1 of the SYSSTAT register is set

so that after a watchdog reset, the ADMC326 can determine that

the reset was due to the timeout of the watchdog timer and not an

external reset. Following a watchdog reset, Bit 1 of the SYSSTAT

This clears the status bit but does not enable the watchdog timer.

On reset, the watchdog timer is disabled and is only enabled when

the first timeout value is written to the WDTIMER register. To

prevent the watchdog timer from timing out, the user must write

to the WDTIMER register at regular intervals (shorter than

the programmed WDTIMER period value). On all but the first

write to WDTIMER, the particular value written to the register

is unimportant since writing to WDTIMER simply reloads the

first value written to this register.

PROGRAMMABLE DIGITAL INPUT/OUTPUT

The ADMC326 has nine programmable digital input/output

(PIO) pins that are all multiplexed with other functions. The

nine PIO lines PIO0–PIO8 are multiplexed with the serial port

(Pins PIO0/TFS1 to PIO5/RFS1), the CLKOUT (Pin PIO6/

CLKOUT) and the auxiliary PWM outputs (Pins PIO7/AUX1

and PIO8/AUX0). When configured as a PIO, each of these

nine pins can act as an input, output, or an interrupt source.

The operating mode of pins PIO0/TFS1 to PIO7/AUX1 is con-

trolled by the PIOSELECT register. This 8-bit register has a bit

for each input so that the mode of each pin may be selected in-

dividually. Bit 0 of PIOSELECT controls the operation of the

PIO0/TFS1 pin. Bit 1 controls the PIO1/DT1 pin, etc. Setting

the appropriate bit in the PIOSELECT register causes the cor-

responding pin to be configured for PIO functionality. Clearing

the bit selects the alternate (SPORT, CLKOUT, or AUXPWM)

Table VIII. Auxiliary PWM Timers

Parameter

Test Conditions

Min

Typ

Max

Unit

Resolution

Bits

PWM Frequency

10 MHz CLKIN

0.039

MHz

mode of the corresponding pin. Following power-on reset, all

bits of PIOSELECT are set such that PIO functionality is

selected. The operating mode of the PIO8/AUX0 pin is selected

by Bit 1 of the PIODATA1 register. In a manner identical to the

PIOSELECT register, setting this bit enables PIO functionality

(PIO8) while clearing the bit enables auxiliary PWM functional-

ity (AUX0).

Once PIO functionality has been selected for any or all of these

nine pins, the direction may be set by the 8-bit PIODIR0 register

(for PIO0 to PIO7) and the 1-bit PIODIR1 register (for PIO8).

Clearing any bit configures the corresponding PIO line as an

input while setting the bit configures it as an output. By default,

following a reset, all bits of PIODIR0 and PIODIR1 are cleared

configuring the PIO lines as inputs.

The data of the PIO0 to PIO8 lines is controlled by the

PIODATA0 register (for PIO0 to PIO7) and Bit 0 of the

PIODATA1 register (for PIO8). These registers can be used

to read data from those PIO lines configured as inputs and

write data to those configured as outputs. Any of the nine pins

that have been configured for PIO functionality can be made

to act as an interrupt source by setting the appropriate bit of the

PIOINTEN0 register (for PIO0 to PIO7) or the PIOINTEN1

must also be configured as an input. An interrupt is generated

upon a change of state (low-to-high transition or high-to-low

transition) on any input that has been configured as an interrupt

source. Following a change of state event on any such input, the

corresponding bit is set in the PIOFLAG0 register (for PIO0 to

PIO7) and PIOFLAG1 (for PIO8) and a common PIO interrupt is

generated. Reading the PIOFLAG0 and PIOFLAG1 registers

permits determining the interrupt source. Reading the PIOFLAG0

and PIOFLAG1 registers automatically clears all bits of the reg-

isters. Following power-on or reset, all bits of PIOINTEN0 and

PIOINTEN1 are cleared so that no interrupts are enabled.

Each PIO line has an internal pull-down resistor so that follow-

ing power-on or reset all nine lines are configured as input PIOs

and will be read as logic lows if left unconnected.

Multiplexing of PIO Lines

The PIO0–PIO5 lines are multiplexed on the ADMC326 with

the functional lines of the serial port, SPORT1. Although the

PIOSELECT register permits individual selection of the function-

ality of each pin, certain restrictions apply when using SPORT1 for

serial communications.

In general, when transmitting and receiving data on the DTI

and DRIB pins, respectively, the PIO0/TFS1 and PIO5/RFS1 pins

must also be selected for SPORT (TFS1 and RFS1) functionality

even if unframed communication is implemented. Therefore,

when using SPORT1 for any type of serial communication, the

minimal setting for PIOSELECT is 0xD8 (i.e., select DTI, DRIB,

RFS1, and TFS1; select PIO7, PIO6, PIO4, PIO3 as digital I/O).

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