REV. 0

ADM1022

–13–

THERM INPUT/OUTPUT

Pin 11 may be configured as an input for a second temperature

sensor by setting Bit 7 of the Configuration Register, or it may

be used as an interrupt output by clearing Bit 7 of the Configu-

ration Register, which is its default condition. The Thermal

Management Input/Output (

THERM) is a logic input/open-

drain output. It can also function as a logic input. If

THERM is

taken low by an external source, the analog output will be forced

to FFh to switch a controlled fan to maximum speed and

FAN_OFF will be negated.

THERM OPERATING MODE

THERM responds only to the “hardware” temperature limits

at addresses 13h, 14h, 17h and 18h, not to the software pro-

grammed limits. The function of these registers was described

earlier with regard to fault tolerant fan speed control.

HARDWARE

TRIP POINT

THERM

ANALOG

OUTPUT

TEMP

PROGRAMMED

VALUE

5

EXT

THERM

INPUT

Figure 16. Operation of

THERM Output

THERM will go low if the hardware temperature limit is exceeded

for three consecutive measurements. It will remain low until the

temperature falls five degrees below the limit for three con-

secutive measurements. While

THERM is low, the analog

output will go to FFh to boost a controlled fan to full speed

and

FAN_OFF will be negated.

When the Fault Tolerant Fan Control state is exited, the analog

FAN_SPD output returns to its previously programmed value,

which may have been changed during the time that the FAN_SPD

output was forced to FFh.

INTERRUPT STRUCTURE

The Interrupt Structure of the ADM1022 is shown in more

detail in Figure 17. As each measurement value is obtained and

stored in the appropriate value register, the value and the limits

from the corresponding limit registers are fed to the high and

low limit comparators. The result of each comparison (1 = out

of limit, 0 = in limit) is routed to the corresponding bit input of

the Interrupt Status Register via a data demultiplexer, and used

to set that bit high or low as appropriate.

The Interrupt Mask Register has bits corresponding to each of

the Interrupt Status Register Bits. Setting an Interrupt Mask Bit

high forces the corresponding Status Bit output low, while set-

ting an Interrupt Mask Bit low allows the corresponding Status

Bit to be asserted. After masking, the status bits are all OR’d

together to produce the

INT output, which will pull low if any

unmasked status bit goes high, i.e., when any measured value

goes out of limit.

The

INT output is enabled when Bit 1 of the Configuration Register

(

INT_Enable) is high, and Bit 2 (INT_Clear) is low.

The

THERM output cannot be cleared nor its interrupt sources

masked.

STATUS

BIT

MASK

BIT

MASK GATING

8

HIGH

LIMIT

VALUE

LOW

LIMIT

FROM

VALUE

AND LIMIT

REGISTERS

1 = OUT

OF

LIMIT

GPI

INT. TEMP

EXT. TEMP2

DIODE 2 FAULT

RESERVED

GPI

EXT. TEMP1

THERM

DIODE 1 FAULT

0

1

2

3

4

5

6

7

MASKING

DATA

FROM BUS

8 MASK BITS

(SAME BIT

ORDER AS

STATUS

REGISTER)

THIS CONNECTION ONLY RELEVANT IF

THERM IS PULLED LOW EXTERNALLY.

D2–/

THERM

CONFIGURATION

REGISTER

INT_ENABLE

INT_CLEAR

INT

HIGH

AND

LOW

LIMIT

COMPARA-

TORS

INTERRUPT

MASK

REGISTER

INTERRUPT

STATUS

REGISTER

DATA

DEMULTI-

PLEXER

Figure 17. Interrupt Register Structure