ADF4110 datasheet(23/24 Pages) AD

23 / 24 page

REV. 0

ADF4110/ADF4111/ADF4112/ADF4113

–23–

INTERFACING

The ADF4110 family has a simple SPI-compatible serial inter-

face for writing to the device. SCLK, SDATA and LE control

the data transfer. When LE (Latch Enable) goes high, the 24 bits

which have been clocked into the input register on each rising

edge of SCLK will get transferred to the appropriate latch. See

Figure 1 for the Timing Diagram and Table I for the Latch

Truth Table.

The maximum allowable serial clock rate is 20 MHz. This means

that the maximum update rate possible for the device is 833 kHz or

one update every 1.2 microseconds. This is certainly more than

adequate for systems that will have typical lock times in hundreds

of microseconds.

ADuC812 Interface

Figure 34 shows the interface between the ADF4110 family and

the ADuC812 microconverter. Since the ADuC812 is based on

an 8051 core, this interface can be used with any 8051-based

microcontroller. The microconverter is set up for SPI Master

Mode with CPHA = 0. To initiate the operation, the I/O port

driving LE is brought low. Each latch of the ADF4110 family

needs a 24-bit word. This is accomplished by writing three 8-bit

bytes from the microconverter to the device. When the third

byte has been written the LE input should be brought high to

complete the transfer.

On first applying power to the ADF4110 family, it needs three

writes (one each to the R counter latch, the N counter latch and

the initialization latch) for the output to become active.

I/O port lines on the ADuC812 are also used to control power-

down (CE input) and to detect lock (MUXOUT configured as

lock detect and polled by the port input).

When operating in the mode described, the maximum SCLOCK

rate of the ADuC812 is 4 MHz. This means that the maximum

rate at which the output frequency can be changed will be

166 kHz.

SCLOCK

MOSI

I/O PORTS

ADuC812

SCLK

SDATA

MUXOUT

(LOCK DETECT)

ADF4110

ADF4111

ADF4112

ADF4113

Figure 34. ADuC812 to ADF4110 Family Interface

ADSP-2181 Interface

Figure 35 shows the interface between the ADF4110 family and

the ADSP-21xx Digital Signal Processor. The ADF4110 family

needs a 24-bit serial word for each latch write. The easiest way

to accomplish this using the ADSP-21xx family is to use the

Autobuffered Transmit Mode of operation with Alternate

Framing. This provides a means for transmitting an entire

block of serial data before an interrupt is generated.

SCLK

I/O FLAGS

ADSP-21xx

SCLK

SDATA

MUXOUT

(LOCK DETECT)

ADF4110

ADF4111

ADF4112

ADF4113

TFS

Figure 35. ADSP-21xx to ADF4110 Family Interface

Set up the word length for 8 bits and use three memory loca-

tions for each 24-bit word. To program each 24-bit latch, store

the three 8-bit bytes, enable the Autobuffered mode and then

write to the transmit register of the DSP. This last operation

initiates the autobuffer transfer.

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