ADF4106 datasheet(3/20 Pages) AD

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–3–

REV. 0

BChips

Parameter

B Version1

(typ)

Unit

Test Conditions/Comments

NOISE CHARACTERISTICS

ADF4106 Phase Noise Floor

–174

dBc/Hz typ

@ 25 kHz PFD Frequency

–166

dBc/Hz typ

@ 200 kHz PFD Frequency

–159

dBc/Hz typ

@ 1 MHz PFD Frequency

Phase Noise Performance

@ VCO Output

900 MHz Output

–93

dBc/Hz typ

@ 1 kHz Offset and 200 kHz PFD Frequency

5800 MHz Output

–74

dBc/Hz typ

@ 1 kHz Offset and 200 kHz PFD Frequency

5800 MHz Output

–84

dBc/Hz typ

@ 1 kHz Offset and 1 MHz PFD Frequency

Spurious Signals

900 MHz Output

–90/–92

dBc typ

@ 200 kHz/400 kHz and 200 kHz PFD Frequency

5800 MHz Output

–65/–70

dBc typ

@ 200 kHz/400 kHz and 200 kHz PFD Frequency

5800 MHz Output

–70/–75

dBc typ

@ 1 MHz/2 MHz and 1 MHz PFD Frequency

NOTES

1Operating temperature range (B Version) is –40

°C to +85°C.

2The BChip specifications are given as typical values.

3Use a square wave for lower frequencies, below the mimimum stated.

4This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency

that is less than this value.

5AV

DD = DVDD = 3 V

6Guaranteed by design. Sample tested to ensure compliance.

A = 25

°C; AV

DD = DVDD = 3 V; P = 16; RFIN = 6.0 GHz

A = 25

°C; AV

DD = DVDD = 3.3 V; R = 16383; A = 63; B = 891; P = 32; RF IN = 6.0 GHz

9The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).

10The phase noise is measured with the EVAL-ADF4106EB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for

the synthesizer (fREFOUT = 10 MHz @ 0 dBm).

11f

REFIN = 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; f RF = 900 MHz; N = 4500; Loop B/W = 20 kHz

12f

REFIN = 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; f RF = 5800 MHz; N = 29000; Loop B/W = 20 kHz

13f

REFIN = 10 MHz; fPFD = 1 MHz; Offset Frequency = 1 kHz; f RF = 5800 MHz; N = 5800; Loop B/W = 100 kHz

Specifications subject to change without notice.

(AVDD = DVDD = 3 V

10%; AVDD

≤ VP ≤ 5.5 V; AGND = DGND = CPGND = 0 V; R

SET = 5.1 k

;

TA = TMIN to TMAX unless otherwise noted.)

CLOCK

DB23 (MSB)

DB22

DB2

DB1 (CONTROL

BIT C2)

DATA

DB0 (LSB)

(CONTROL BIT C1)

Figure 1. Timing Diagram

TIMING CHARACTERISTICS

Limit at

TMIN to TMAX

Parameter

(B Version)

Unit

Test Conditions/Comments

ns min

DATA to CLOCK Setup Time

ns min

DATA to CLOCK Hold Time

ns min

CLOCK High Duration

ns min

CLOCK Low Duration

ns min

CLOCK to LE Setup Time

ns min

LE Pulsewidth

Guaranteed by design but not production tested.

ADF4106

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