AD9853

–5–

REV. C

Table I. Modulator Function Description

Modulation Encoding Format

FSK*, QPSK, DQPSK, 16-QAM, D16-QAM, Selectable via Control Bus

Output Carrier Frequency Range

DC – 63 MHz with +3.3 V Supply Voltage

DC – 84 MHz with +5 V Supply Voltage

Serial Input Data Rate

Evenly Divisible Fraction of Reference Clock

Pulse-Shaping FIR Filter

41 Tap, Linear Phase, 10-Bit Coefficients Fully Programmable via Control Bus

Interpolation Range

Interpolation Rate = (4/M)

× (ICIC1) × (ICIC2) where: M = 2 for QPSK, M = 4 for 16-QAM

Minimum and Maximum Rates

Minimum Interpolation Rate—QPSK = 2

× 3 × 2 = 12

16-QAM = 1

× 4 × 3 = 12

Maximum Interpolation Rate—QPSK = 2

× 31 × 63 = 3906

16-QAM = 1

× 31 × 63 = 1953

These are the minimum and maximum interpolation ratios from the input data rate to the

system clock. The interpolation range is a function of the fixed interpolation factor of four

in the FIR filters, the programmed CIC filter interpolation rates (ICIC1, ICIC2), as well

as system timing constraints.

Maximum Reference Clock Frequency

+3.3 V Supply: 21 MHz with 6

× REFCLK enabled, 126 MHz with 6× REFCLK disabled

+5 V Supply: 28 MHz with 6

× REFCLK enabled, 168 MHz with 6× REFCLK disabled

6

× REFCLK

Fixed 6

× reference clock multiplier, enable/disable control via control bus

R-S FEC

Enable/disable via control bus and dedicated control pin. Control pin enable/disable function:

Logic “1” = Enable

Logic “0” = Disable

Code Generator Polynomial: g(x) = (x +

Selectable via Control Bus

t = 0–10 (Programmable)

Codeword Length (N) = 255 max (Programmable)

N = K + 2 t (K Range = 16

≤ K ≤ 255 – 2 t)

FEC/Randomizer can be transposed in signal chain via control bus.

I/Q Channel Spectrum

I

× COS + Q × SIN (default) or I × COS – Q × SIN, selectable via control bus.

Preamble Insertion

0–96 Bits, Programmable Length and Content

Randomizer

Enable/Disable Control via Control Bus

Generating Polynomial:

x

or

Randomizer and FEC blocks can be transposed in signal chain, via control bus.

*In FSK mode, F0:F1 are direct DDS Cosine output. The two interpolator stages of the AD9853 are not used in the FSK mode and should be programmed for

maximum interpolation rates to reduce unnecessary current consumption. This means that Interpolator #1 should be set to a decimal value of 31, and Interpolator

#2 should be set to decimal value of 63. This is easily accomplished by programming Registers 12 and 13 (hex) with the values of FF (hex).