AD9852AST datasheet(26/42 Pages) AD

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AD9852

–26–

REV. 0

Interfacing and Programming the AD9852

The AD9852 Register Layout, shown in Table V, contains the

information that programs the chip for the desired functionality.

While many applications will require very little programming to

conﬁgure the AD9852, some will make use of all twelve acces-

sible register banks. The AD9852 supports an 8-bit byte parallel

I/O operation or an SPI-compatible serial I/O operation. All

accessible registers can be written and read back in either

I/O operating mode.

An external pin, S/P SELECT, is used to conﬁgure the I/O mode.

Systems that use the parallel I/O mode must connect the S/P

SELECT pin to VDD. Systems that operate in the serial I/O mode

must tie the S/P SELECT pin to GND.

Regardless of mode, the I/O port data is written to a buffer

memory that does NOT affect operation of the part until the

contents of the buffer memory are transferred to the register

banks. This transfer of information occurs, synchronously, to the

system clock and occurs in one of two ways:

A<5:0>

D<7:0>

TRDHOZ

TRDLOV

TAHD

TADV

SPECIFICATION

VALUE

DESCRIPTION

TADV

TAHD

TRDLOV

TRDHOZ

ADDRESS TO DATA VALID TIME (MAXIMUM)

ADDRESS HOLD TIME TO RD SIGNAL INACTIVE (MINIMUM)

RD LOW TO OUTPUT VALID (MAXIMUM)

RD HIGH TO DATA THREE-STATE (MAXIMUM)

Figure 49. Parallel Port Read Timing Diagram

D<7:0>

SPECIFICATION

VALUE

DESCRIPTION

TASU

TDSU

TADH

TDHD

4ns

2ns

ADDRESS SETUP TIME TO

WR SIGNAL ACTIVE

DATA SETUP TIME TO

WR SIGNAL INACTIVE

5ns

0ns

ADDRESS HOLD TIME TO

WR SIGNAL INACTIVE

DATA HOLD TIME TO

WR SIGNAL INACTIVE

TWRLOW

TWRHIGH

TWR

3ns

WR SIGNAL MINIMUM LOW TIME

7ns

3ns

WR SIGNAL MINIMUM HIGH TIME

WR SIGNAL MINIMUM PERIOD

A<5:0>

TASU

TAHD

TWRHIGH

TWRLOW

TDHD

TDSU

TWR

Figure 50. Parallel Port Write Timing Diagram

1. Internally, controlled at a rate programmable by the user or,

2. Externally, controlled by the user. I/O operations can occur in

the absence of REFCLK but the data cannot be moved from

the buffer memory to the register bank without REFCLK.

See the Update Clock Operation section of this document

for details.

Parallel I/O Operation

With the S/P SELECT pin tied high, the parallel I/O mode is

active. The I/O port is compatible with industry standard DSPs

and microcontrollers. Six address bits, eight bidirectional data

bits and separate write/read control inputs make up the I/O

port pins.

Parallel I/O operation allows write access to each byte of any

for each register is included to ease designing with the AD9852.

Reads are not guaranteed at 100 MHz as they are intended for

software debug only.

Parallel I/O operation timing diagrams are shown in the Figures

49 and 50.

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