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AD9849 датащи(PDF) 6 Page - Analog Devices

номер детали AD9849
подробное описание детали  CCD Signal Processors with Integrated Timing Driver
PDF  36 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD9849 датащи(HTML) 6 Page - Analog Devices

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REV. 0
–6–
AD9848/AD9849
TIMING SPECIFICATIONS
(CL = 20 pF, fCLI = 20 MHz [AD9848] or 30 MHz [AD9849], Serial Timing in Figure 3, unless
otherwise noted.)
Parameter
Symbol
Min
Typ
Max
Unit
MASTER CLOCK (CLI), AD9848
CLI Clock Period
tCLI
50
ns
CLI High/Low Pulsewidth
tADC
25
ns
Delay From CLI to Internal Pixel Period Position
tCLIDLY
6ns
MASTER CLOCK (CLI), AD9849
CLI Clock Period
tCONV
33.33
ns
CLI High/Low Pulsewidth
tADC
16.67
ns
EXTERNAL MODE CLAMPING
CLPDM Pulsewidth
tCDM
4
10
Pixels
CLPOB Pulsewidth
1
tCOB
2
20
Pixels
SAMPLE CLOCKS
SHP Rising Edge to SHD Rising Edge (AD9848)
tS1
20
ns
SHP Rising Edge to SHD Rising Edge (AD9849)
tS1
13
ns
DATA OUTPUTS
Output Delay from Programmed Edge
tOD
6ns
Pipeline Delay
9
Cycles
SERIAL INTERFACE
Maximum SCK Frequency
fSCLK
10
MHz
SL to SCK Setup Time
tLS
10
ns
SCK to SL Hold Time
tLH
10
ns
SDATA Valid to SCK Rising Edge Setup
tDS
10
ns
SCK Falling Edge to SDATA Valid Hold
tDH
10
ns
SCK Falling Edge to SDATA Valid Read
tDV
10
ns
NOTES
1Maximum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp reference.
Specifications subject to change without notice.



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