AD9840A

–9–

REV. 0

SERIAL INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION

Table I. Internal Register Map

Register

Address

Data Bits

Name

A0

A1 A2

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

Operation

0

0

0

Channel Select

Power-Down

Software OB Clamp 0

*

1

**

0

*

0

*

0

*

CCD/AUX

Modes

Reset

On/Off

VGA Gain

1

0

0

LSB

MSB

X

Clamp Level

0

1

0

LSB

MSB

X

X

X

Control

1

1

0

0

*

0

*

0

*

CDS Gain Clock Polarity Select for

0

*

0

*

Three-

X

On/Off

SHP/SHD/CLP/DATA

State

CDS Gain

0

0

1

LSB

MSB

X

X

X

X

X

SDATA

SCK

SL

RNW

TEST

0

A2

0

A0

A1

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

NOTES:

1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK.

2. RNW = READ-NOT WRITE. SET LOW FOR WRITE OPERATION.

3. TEST BIT = INTERNAL USE ONLY. MUST BE SET LOW.

4. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE.

Figure 8. Serial Write Operation

SDATA

SCK

SL

RNW

TEST

10

A0

A1

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

NOTES:

1. RNW = READ-NOT WRITE. SET HIGH FOR READ OPERATION.

2. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW.

3. SERIAL DATA FROM THE SELECTED REGISTER IS VALID STARTING AFTER THE 5TH SCK FALLING EDGE, AND IS UPDATED ON SCK

FALLING EDGES.

A2

Figure 9. Serial Readback Operation

SDATA

SCK

SL

A0

A1

D0

D2

D3

D10

RNW

0

0

D9

0

00

D0

1

217

35

34

27

26

16

6

5

4

3

44

...

...

...

...

10 BITS

AGC GAIN

D7

D0

D9

...

...

...

...

...

NOTES:

1. ANY NUMBER OF ADJACENT REGISTERS MAY BE LOADED SEQUENTIALLY, BEGINNING WITH THE LOWEST ADDRESS AND INCREMENTING

ONE ADDRESS AT A TIME.

2. WHEN SEQUENTIALLY LOADING MULTIPLE REGISTERS, THE EXACT REGISTER LENGTH (SHOWN ABOVE) MUST BE USED FOR EACH REGISTER.

3. ALL LOADED REGISTERS WILL BE SIMULTANEOUSLY UPDATED WITH THE RISING EDGE OF SL.

8 BITS

CLAMP LEVEL

10 BITS

CONTROL

11 BITS

OPERATION

D1

D0

D2

D3

D1

18

19

20

78

9

Figure 10. Continuous Serial Write Operation to Multiple Registers