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AD9834 датащи(PDF) 3 Page - Analog Devices

номер детали AD9834
подробное описание детали  Low Power, 2.3 V to 5.5 V, 50 MHz Complete DDS
PDF  20 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD9834 датащи(HTML) 3 Page - Analog Devices

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AD9834
–3–
REV PrM
PRELIMINARY TECHNICAL DATA
TIMINGCHARACTERISTICS1 (V
DD = +2.3 V to +5.5 V; AGND = DGND = 0 V, unless otherwise noted)
Parameter
Limit at TMIN to TMAX
Units
Test Conditions/Comments
t1
20
ns min
MCLK Period
t2
8
ns min
MCLK High Duration
t3
8
ns min
MCLK Low Duration
t4
25
ns min
SCLK Period
t5
10
ns min
SCLK High Duration
t6
10
ns min
SCLK Low Duration
t7
5
ns min
FSYNC to SCLK Falling Edge Setup Time
t8
10
ns min
FSYNC to SCLK Hold Time
t4 - 5
ns max
t9
5
ns min
Data Setup Time
t10
3
ns min
Data Hold Time
t11
8
ns min
FSELECT, PSELECT Setup Time Before MCLK Rising Edge
t11A
*
8
ns min
FSELECT, PSELECT Setup Time After MCLK Rising Edge
1 Guaranteed by design, not production tested.
*See Pin Description Section.
Figure 3. Control Timing
Figure 2. Master Clock
Figure 4. Serial Timing
Figure 1. Test Circuit With which Specifications are tested.
IOUT
COMP
FS
ADJUST
REFOUT
12
AD9834
ON-BOARD
REFERENCE
10-BIT DAC
SIN
ROM
FULL-SCALE
CONTROL
200R
20pF
RSET
6.8 K
10nF
10nF
AVDD
REGULATOR
100nF
CAP/2.5V
MCLK
t2
t1
t3
t11A
t11
VALIDDATA
VALID DATA
VALIDDATA
MCLK
FSELECT,
PSELECT
SCLK
FSYNC
SDATA
t5
t4
t6
t7
t8
t10
t9
D15
D14
D2
D1
D0
D15
D14



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