AD9830AST datasheet(9/16 Pages) AD

9 / 16 page

AD9830

REV. A

–9–

RBW 1kHz

VBW 3kHz

ST 50 SEC

–10

–90

START 0Hz

STOP 25MHz

–40

–60

–70

–80

–20

–30

–50

Figure 17. fMCLK = 50 MHz, fOUT = 16.5 MHz, Frequency

Word = 547AE148

Size

Description

FREQ0 REG

32 Bits

Frequency Register 0. This defines

the output frequency, when

FSELECT = 0, as a fraction of the

MCLK frequency.

FREQ1 REG

32 Bits

Frequency Register 1. This de-

fines the output frequency, when

FSELECT = 1, as a fraction of the

MCLK frequency.

PHASE0 REG

12 Bits

Phase Offset Register 0. When

PSEL0 = PSEL1 = 0, the contents

of this register are added to the out-

put of the phase accumulator.

PHASE1 REG

12 Bits

Phase Offset Register 1. When

PSEL0 = 1 and PSEL1 = 0, the

contents of this register are added

to the output of the phase

accumulator.

PHASE2 REG

12 Bits

Phase Offset Register 2. When

PSEL0 = 0 and PSEL1 = 1, the

contents of this register are added

to the output of the phase

accumulator.

PHASE3 REG

12 Bits

Phase Offset Register 3. When

PSEL0 = PSEL1 = 1, the contents

of this register are added to the out-

put of the phase accumulator.

Figure 18. AD9830 Control Registers

Destination Register

FREQ0 REG 16 LSBs

FREQ0 REG 16 MSBs

FREQ1 REG 16 LSBs

FREQ1 REG 16 MSBs

PHASE0 REG

PHASE1 REG

PHASE2 REG

PHASE3 REG

Figure 19. Addressing the Control Registers

D15

MSB

LSB

Figure 20. Frequency Register Bits

D15

D14 D13 D12 D11

XXXMSB

LSB

X = Don't Care

Figure 21. Phase Register Bits

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