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AD9826

–18–

REV. A

TOP VIEW

(Not to Scale)

AD9826

CDSCLK1

CDSCLK2

ADCCLK

OEB

DRVDD

DRVSS

(MSB) D7

(LSB)D0

AVDD

AVSS

VINR

OFFSET

VING

CML

VINB

CAPT

CAPB

AVSS

AVDD

SLOAD

SCLK

SDATA

0.1 F

10 F

0.1 F

RED INPUT

GREEN INPUT

BLUE INPUT

CLOCK

INPUTS

0.1 F

DATA

INPUTS

5V/3V

0.1 F

1.0 F

0.1 F

SERIAL

INTERFACE

Figure 18. Recommended Circuit Configuration, 3-Channel CDS Mode

Programmable Gain Amplifiers

The AD9826 uses one Programmable Gain Amplifier (PGA) for

each channel. Each PGA has a gain range from 1

× (0 dB) to

6.0

× (15.56 dB), adjustable in 64 steps. Figure 17 shows the

PGA gain as a function of the PGA register code. Although the

gain curve is approximately “linear in dB,” the gain in V/V var-

ies nonlinearly with register code, following the equation:

Gain













15 0

–

where G is the decimal value of the gain register contents, and

varies from 0 to 63.

PGA REGISTER VALUE – Decimal

GAIN – V/V

GAIN – dB

1.00

2.25

4.75

3.50

6.00

Figure 17. PGA Gain Transfer Function

APPLICATIONS INFORMATION

Circuit and Layout Recommendations

The recommended circuit configuration for 3-Channel CDS

Mode operation is shown in Figure 18. The recommended

input coupling capacitor value is 0.1

µF (see Circuit Operation

section for more details). A single ground plane is recommended

for the AD9826. A separate power supply may be used for

DRVDD, the digital driver supply, but this supply pin should

still be decoupled to the same ground plane as the rest of the

AD9826. The loading of the digital outputs should be mini-

mized, either by using short traces to the digital ASIC, or by

using external digital buffers. To minimize the effect of digital

transients during major output code transitions, the falling edge

of CDSCLK2 should occur coincident with or before the

rising edge of ADCCLK (see Figures 1 through 6 for timing).

All 0.1

µF decoupling capacitors should be located as close as

possible to the AD9826 pins. When operating in 1CH or 2CH

Mode, the unused analog inputs should be grounded.

For 3-Channel SHA Mode, all of the above considerations also

apply, except that the analog input signals are directly connected

to the AD9826 without the use of coupling capacitors. The analog

input signals must already be dc-biased between 0 V and 4 V.

Also, the OFFSET pin should be grounded if the inputs to the

AD9826 are to be referenced to ground, or a dc offset voltage

should be applied to the OFFSET pin in the case where a coarse

offset needs to be removed from the inputs. (See Figure 16 and

the Circuit Operation section for more details.)

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