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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9822 датащи(PDF) 3 Page - Analog Devices |
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AD9822 датащи(HTML) 3 Page - Analog Devices |
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3 / 15 page  –3– REV. A DIGITAL SPECIFICATIONS Parameter Symbol Min Typ Max Unit LOGIC INPUTS High Level Input Voltage VIH 2.0 V Low Level Input Voltage VIL 0.8 V High Level Input Current IIH 10 µA Low Level Input Current IIL 10 µA Input Capacitance CIN 10 pF LOGIC OUTPUTS High Level Output Voltage VOH 4.5 V Low Level Output Voltage VOL 0.1 V High Level Output Current IOH 50 µA Low Level Output Current IOL 50 µA Specifications subject to change without notice. TIMING SPECIFICATIONS Parameter Symbol Min Typ Max Unit CLOCK PARAMETERS 3-Channel Pixel Rate tPRA 67 ns 1-Channel Pixel Rate tPRB 80 ns ADCCLK Pulsewidth tADCLK 30 ns CDSCLK1 Pulsewidth tC1 10 ns CDSCLK2 Pulsewidth tC2 10 ns CDSCLK1 Falling to CDSCLK2 Rising tC1C2 0ns ADCCLK Falling to CDSCLK2 Rising tADC2 0ns CDSCLK2 Rising to ADCCLK Rising tC2ADR 0ns CDSCLK2 Falling to ADCCLK Falling tC2ADF 30 40 ns CDSCLK2 Falling to CDSCLK1 Rising tC2C1 30 40 ns ADCCLK Falling to CDSCLK1 Rising tADC1 0ns Aperture Delay for CDS Clocks tAD 2ns SERIAL INTERFACE Maximum SCLK Frequency fSCLK 10 MHz SLOAD to SCLK Setup Time tLS 10 ns SCLK to SLOAD Hold Time tLH 10 ns SDATA to SCLK Rising Setup Time tDS 10 ns SCLK Rising to SDATA Hold Time tDH 10 ns SCLK Falling to SDATA Valid tRDV 10 ns DATA OUTPUT Output Delay tOD 8ns 3-State to Data Valid tDV 10 ns Output Enable High to 3-State tHZ 10 ns Latency (Pipeline Delay) 3 (Fixed) Cycles Specifications subject to change without notice. (TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V, CDS Mode, fADCCLK = 15 MHz, fCDSCLK1 = fCDSCLK2 = 5 MHz, CL = 10 pF, unless otherwise noted.) (TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V) NOTES 1Linear input signal range is from 2 V to 4 V when the CCD’s reference level is clamped to 4 V by the AD9822’s input clamp. 1V TYP RESET TRANSIENT 4V SET BY INPUT CLAMP (3V OPTION ALSO AVAILABLE) 2V p-p MAX INPUT SIGNAL RANGE 2The PGA Gain is approximately “linear in dB” and follows the equation: Gain = + [ . .[ ] ] 57 14 7 63 –G 63 where G is the register value. See Figure 13. Specifications subject to change without notice. AD9822 |
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