AD9803 datasheet(13/19 Pages) AD

13 / 19 page

AD9803

–13–

REV. 0

Even-Odd Pixel Offset Correction

The AD9803 includes digital correction circuitry following the

10-bit ADC. The purpose of the digital correction is remove

the residual offset between the even and odd pixel channels,

which results from the “ping-pong” CDS architecture of the

AD9803. The digital offset correction tracks the black level of

the even and odd channels, applying the necessary digital cor-

rection value to keep them balanced. There is an additional two

cycle delay when using the offset correction, resulting in pipe-

line delay of 7 ADCCLK cycles (see Figure 1).

A/D

CONVERTER

EVEN

ODD

2:1

MUX

ADCCLK

DIGITAL

OFFSET

CORRECTION

DOUT

CLPOB

Figure 32. Digital Offset Correction

Auxiliary DACs

The AD9803 includes two 8-bit DACs for controlling any off-

chip system functions. These are voltage output DACs with

near rail-to-rail output capability. Output voltage levels are

programmed through the serial interface. DAC specifications

are shown on page 4, and the DAC equivalent output circuit is

shown in Figure 14.

AUX-MODE Operation

In addition to the CCD signal-processing path, the AD9803

includes an analog video-processing path. The AUXIN (Pin 34)

input consists of an input clamp, PGA, and ADC. Figure 33

shows the Input Configuration of this mode. The recommended

value of the external ac-coupling capacitor is 0.1

µF. The volt-

age droop with this capacitor value is 20

µV/µs.

The recommended method of controlling the input clamp is

to simply ground the ACLP input (Pin 15) to activate the

“automatic” clamping capability of the AD9803. The clamp

may also be controlled with a separate clock signal. See the

clamp timing in Figure 4 for more details.

The THD performance for fS = 18 MHz is shown in Figure 21.

When operating at fS = 18 MHz, the linearity performance is

comparable to the CCD-Mode linearity, shown in Figure 18.

The AUX-MODE can be operated at a sampling rate of up to

28.6 MHz. If the sample rate exceeds 18 MHz, then the High

Speed AUX-MODE should be programmed through the serial

interface (D-Register 01).

AUXIN

CLP

ACLP

PGA

SHA

CLAMP LEVEL (E-REG)

–

0.1 F

VIDEO

SIGNAL

GND

AD9803

0~10 dB

ADCCLK

2 A

ADC

LPF

AUX

CONT

0.1 F

Figure 33. AUX-MODE Circuit Configuration

ADC-MODE Operation

The ADC-MODE of operation is the same as the AUX-MODE,

except there is no PGA in the signal path, only the input clamp

and ADC. Input specifications and timing for ADC-MODE are

the same as those for AUX-MODE. The THD performance is

shown in Figure 22.

AD9803 датащи(PDF) 13 Page - Analog Devices

AD9803 датащи(HTML) 13 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

датащи скачать

ссылки URL