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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9777EB датащи(PDF) 21 Page - Analog Devices |
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AD9777EB датащи(HTML) 21 Page - Analog Devices |
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21 / 48 page  REV. 0 AD9777 –21– CHARGE PUMP PHASE DETECTOR CLK+ CLOCK DISTRIBUTION CIRCUITRY VCO AD9777 CLK– SPI PORT INTERNAL SPI CONTROL REGISTERS PLL_LOCK 1 = LOCK 0 = NO LOCK PLLVDD LPF INTERPOLATION FILTERS, MODULATORS, AND DACS 2 8 INTERPOLATION RATE CONTROL PLL DIVIDER (PRESCALER) CONTROL PLL CONTROL (PLL ON) 1 INPUT DATA LATCHES MODULATION RATE CONTROL PRESCALER 4 Figure 12. PLL and Clock Circuitry with PLL Enabled CHARGE PUMP PHASE DETECTOR CLK+ CLOCK DISTRIBUTION CIRCUITRY VCO AD9777 CLK– SPI PORT INTERNAL SPI CONTROL REGISTERS PLL_LOCK 1 = LOCK 0 = NO LOCK INTERPOLATION FILTERS, MODULATORS, AND DACS 2 8 INTERPOLATION RATE CONTROL PLL DIVIDER (PRESCALER) CONTROL PLL CONTROL (PLL ON) 1 INPUT DATA LATCHES MODULATION RATE CONTROL PRESCALER 4 Figure 13. PLL and Clock Circuitry with PLL Disabled In addition, if the zero stuffing option is enabled, the VCO will double its speed again. Phase noise may be slightly higher with the PLL enabled. Figure 14 illustrates typical phase noise per- formance of the AD9777 with 2 × interpolation and various input data rates. The signal synthesized for the phase noise measurement was a single carrier at a frequency of fDATA/4. The repetitive nature of this signal eliminated quantization noise and distortion spurs as a factor in the measurement. Although the curves blend together in Figure 14, the different conditions are called out here for clarity. fDATA PLL Prescaler Ratio 125 MSPS Disabled 125 MSPS Enabled div1 100 MSPS Enabled div2 75 MSPS Enabled div2 50 MSPS Enabled div4 FREQUENCY OFFSET – MHz –80 0 0 –70 –60 –50 –40 –30 –20 –10 –90 –110 –100 12 3 4 5 Figure 14. Phase Noise Performance It is important to note that the resistor/capacitor needed for the PLL loop filter is internal on the AD9777. This will suffice unless the input data rate is below 10 MHz, in which case an external series RC is required between the LPF and PLLVDD Pins. POWER DISSIPATION The AD9777 has three voltage supplies: AVDD, DVDD, and CLKVDD. Figures 15, 16, and 17 show the current required from each of these supplies when each is set to the 3.3 V nomi- nal specified for the AD9777. Power dissipation (PD) can easily be extracted by multiplying the given curves by 3.3. As Figure 15 shows, IDVDD is very dependent on the input data rate, the interpolation rate, and the activation of the internal digital modulator. IDVDD, however, is relatively insensitive to the modulation rate by itself. In Figure 16, IAVDD shows the same type of sensitivity to data, interpolation rate, and the modulator function but to a much lesser degree (<10%). In Figure 17, ICLKVDD varies over a wide range yet is responsible for only a small percentage of the overall AD9777 supply current requirements. fDATA – MHz 050 0 100 150 200 50 100 150 200 250 300 350 400 8 (MOD. ON) , 4 (MOD. ON) , 2 (MOD. ON) , 8 4 2 1 Figure 15. IDVDD vs. fDATA vs. Interpolation Rate, PLL Disabled |
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