AD9772AAST datasheet(15/32 Pages) AD

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REV. A

AD9772A

–15–

latched into the AD9772 on every other rising edge of the differ-

ential clock input. The rising edge that corresponds to the input

latch immediately precedes the rising edge of the 1

clock at

PLLLOCK. Adequate setup and hold time for the input data as

shown in Figure 1b should be allowed. Note that enough delay

is present between CLK+/CLK– and the data input latch to

cause the minimum setup time for input data to be negative.

This is noted in the Digital Specifications section. PLLLOCK

contains a relatively weak driver output, with its output delay

(tOD) sensitive to output capacitance loading. Thus PLLLOCK

should be buffered for fanouts greater than one, and/or load

capacitance greater than 10 pF. If a data timing issue exists

between the AD9772A and its external driver device, the 1

clock appearing at PLLLOCK can be inverted via an external

gate to ensure proper setup and hold time.

CHARGE

PUMP

PHASE

DETECTOR

EXT/INT

CLOCK CONTROL

PRESCALER

CLKVDD

OUT1

CLKCOM

MOD1 MOD0 RESET

CLK+

LPF

PLL

VDD

PLL

COM

DIV1

DIV0

CLOCK

DISTRIBUTION

–

PLLLOCK

CLK–

VCO

AD9772A

Figure 11. Clock Multiplier with PLL Clock Multiplier

Disabled

SYNCHRONIZATION OF CLK/DATA USING RESET WITH

PLL DISABLED

The relationship between the internal and external clocks in this

mode is shown in Figure 12. A clock at the output update data

rate (2

the input data rate) must be applied to the CLK in-

puts. Internal dividers create the internal 1

clock necessary for

the input latches. With the PLL disabled, a delayed version of the

clock is present at the PLLLOCK pin. The DAC latch is

updated on the particular rising edge of the external 2

clock

which corresponds to the rising edge of the 1

clock. Updates

to the input data should be synchronized to this specific rising

edge as shown in Figure 12. To ensure this synchronization, a

Logic 1 should be momentarily applied to the RESET pin on

power up, before CLK is applied. Applying a momentary Logic 1

to RESET brings the 1

clock at PLLLOCK to a Logic 1. On

the next rising edge of the 2

clock, the 1

clock will go to

Logic 0. The following rising edge of the 2

clock will cause

the 1

clock to Logic 1 again, as well as update the data in

both of the input latches.

DIGITAL DATA IN

EXTERNAL

CLK

DELAYED INTERNAL

CLK

LOAD DEPENDENT

DELAYED 1

CLK

AT PLLLOCK

IOUTA OR IOUTB

DATA

tLPW

tPD

DATA ENTERS INPUT

LATCHES ON THIS EDGE

Figure 12. Internal Timing of AD9772A with PLL Disabled

Figure 13 illustrates the details of the RESET function timing.

RESET going from a high to a low logic level enables the 1

clock output, generated by the PLLLOCK pin. If RESET goes

low at a time well before the rising edge of the 2

clock, then

PLLLOCK will go high on the following edge of the 2

clock. If

RESET goes from a high to a low logic level 600 ps or later

following the rising edge of the 2

× clock, there will be a delay of

one 2

clock cycle before PLLLOCK goes high. In either case,

as long as RESET remains low, PLLLOCK will change state on

every rising edge of the 2

clock. As stated before, it is the rising

edge of the 2

clock which immediately precedes the rising edge

of PLLLOCK that latches data into the AD9772A input latches.

CH1 2.00V

CH2 2.00V

M 10.0ns CH3 2.00V

[ T

]

CH1 2.00V

CH2 2.00V

M 10.0ns CH4

1.20V

CH3 2.00V

Figure 13. RESET Timing of AD9772A with PLL Disabled

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