AD9761ARS datasheet(14/23 Pages) AD

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AD9761

–14–

REV. A

ensure proper compatibility of most TTL logic families. Figure

31 shows the equivalent digital input circuit for the data, sleep

and clock inputs.

RESET

DATA

SELECT

CLOCK/WRITE

Figure 30. Timing Diagram

DVDD

DIGITAL

INPUT

Figure 31. Equivalent Digital Input

Since the AD9761 is capable of being updated up to 40 MSPS,

the quality of the clock and data input signals are important in

achieving the optimum performance. The drivers of the digital

data interface circuitry should be specified to meet the mini-

mum setup and hold-times of the AD9761 as well as its re-

quired min/max input logic level thresholds. The external clock

driver circuitry should provide the AD9761 with a low jitter

clock input meeting the min/max logic levels while providing

fast edges. Fast clock edges will help minimize any jitter that can

manifest itself as phase noise on a reconstructed waveform.

Digital signal paths should be kept short, and run lengths

matched to avoid propagation delay mismatch. The insertion of

a low value resistor network (i.e., 20

Ω to 100 Ω) between the

AD9761 digital inputs and driver outputs may be helpful in

reducing any overshooting and ringing at the digital inputs,

which contributes to data feedthrough. Operating the AD9761

with reduced logic swings and a corresponding digital supply

(DVDD) will also reduce data feedthrough.

RESET/SLEEP MODE OPERATION

The RESET/SLEEP input can be used either to power-down

the AD9761 or reset its internal digital interface logic. If the

RESET/ SLEEP input is asserted for greater than one clock

cycle but under four clock cycles by applying a logic level “1,”

the internal state machine will be reset. If the RESET/SLEEP

input is asserted for four clock cycles or longer, the power-down

function of the AD9761 will be initiated. The power-down

function turns off the output current and reduces the supply

current to less than 9 mA over the specified supply range of

2.7 V to 5.5 V and temperature range.

The power-up and power-down characteristics of the AD9761 is

dependent upon the value of the compensation capacitor con-

nected to COMP1 and COMP3. With a nominal value of 0.1

µF,

the AD9761 takes less than 5

µs to power down and approxi-

mately 3.25 ms to power back up.

POWER DISSIPATION

The power dissipation of the AD9761 is dependent on several

factors which include: (1) AVDD and DVDD, the power supply

voltages; (2) IOUTFS, the full-scale current output; (3) fCLOCK, the

update rate; (4) and the reconstructed digital input waveform.

The power dissipation is directly proportional to the analog

supply current, IAVDD, and the digital supply current, IDVDD.

IAVDD is directly proportional to IOUTFS as shown in Figure 32

and is insensitive to fCLOCK.

IOUTFS – mA

110

456

789

Figure 32. IAVDD vs. IOUTFS

Conversely, IDVDD is dependent on both the digital input wave-

form, fCLOCK, and digital supply DVDD. Figures 33 and 34 show

IDVDD as a function of a full-scale sine wave output ratio’s (fOUT/

fCLOCK) for various update rate with DVDD = 5 V and DVDD =

3 V respectively.

5 MSPS

RATIO – fOUT/fCLK

0.05

0.15

40 MSPS

0.1

20 MSPS

10 MSPS

0.2

2.5 MSPS

Figure 33. IDVDD vs. Ratio @ DVDD = 5 V

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