REV. 0

AD9740

–13–

AD9740 while meeting other system level objectives (i.e., cost,

power) should be selected. The op amp’s differential gain, its gain

setting resistor values, and full-scale output swing capabilities

should all be considered when optimizing this circuit.

The differential circuit shown in Figure 12 provides the necessary

level shifting required in a single-supply system. In this case,

AVDD, which is the positive analog supply for both the AD9740

and the op amp, is also used to level shift the differential output

of the AD9740 to midsupply (i.e., AVDD/2). The AD8041 is a

suitable op amp for this application.

AD9740

IOUTA

IOUTB

500

225

225

1k

25

25

AD8041

1k

AVDD

Figure 12. Single-Supply DC Differential Coupled Circuit

SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT

Figure 13 shows the AD9740 configured to provide a unipolar

output range of approximately 0 V to 0.5 V for a doubly termi-

nated 50

Ω cable, since the nominal full-scale current, I

Ω. In this

IOUTA or IOUTB. The unused output (IOUTA or IOUTB)

the positive compliance range is adhered to. One additional

consideration in this mode is the integral nonlinearity (INL) as

discussed in the Analog Output section of this data sheet. For

optimum INL performance, the single-ended, buffered voltage

output configuration is suggested.

AD9740

IOUTA

IOUTB

50

25

50

Figure 13. 0 V to 0.5 V Unbuffered Voltage Output

SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT

CONFIGURATION

Figure 14 shows a buffered single-ended output configuration in

which the op amp U1 performs an I-V conversion on the AD9740

output current. U1 maintains IOUTA (or IOUTB) at a virtual

ground, minimizing the nonlinear output impedance effect on the

DAC’s INL performance as discussed in the Analog Output

section. Although this single-ended configuration typically

provides the best dc linearity performance, its ac distortion

performance at higher DAC update rates may be limited by

U1’s slew rate capabilities. U1 provides a negative unipolar output

An improvement in ac distortion performance may result with a

AD9740

IOUTA

IOUTB

200

U1

200

Figure 14. Unipolar Buffered Voltage Output

POWER AND GROUNDING CONSIDERATIONS,

POWER SUPPLY REJECTION

Many applications seek high speed and high performance under

less than ideal operating conditions. In these application circuits,

the implementation and construction of the printed circuit board

is as important as the circuit design. Proper RF techniques must

be used for device selection, placement, and routing as well as power

supply bypassing and grounding to ensure optimum performance.

Figures 19 to 22 illustrate the recommended printed circuit board

ground, power, and signal plane layouts that are implemented on

the AD9740 evaluation board.

One factor that can measurably affect system performance is the

ability of the DAC output to reject dc variations or ac noise

superimposed on the analog or digital dc power distribution.

This is referred to as the power supply rejection ratio. For dc

variations of the power supply, the resulting performance of the

DAC directly corresponds to a gain error associated with the

common in applications where the power distribution is gener-

ated by a switching power supply. Typically, switching power

supply noise will occur over the spectrum from tens of kHz to

several MHz. The PSRR vs frequency of the AD9740 AVDD

supply over this frequency range is shown in Figure 15.

FREQUENCY – MHz

85

40

12

6

0

80

75

70

65

60

55

50

24

8

10

45

Figure 15. Power Supply Rejection Ratio

Note that the units in Figure 15 are given in units of (amps out/

volts in). Noise on the analog power supply has the effect of

modulating the internal switches, and therefore the output current.

The voltage noise on AVDD, therefore, will be added in a

nonlinear manner to the desired IOUT. Due to the relative differ-

ent size of these switches, PSRR is very code dependent. This

can produce a mixing effect that can modulate low-frequency

power supply noise to higher frequencies. Worst-case PSRR for

either one of the differential DAC outputs will occur when the