AD9432SLASHPCB datasheet(6/20 Pages) AD

6 / 20 page

REV. E

AD9432

–6–

Spurious-Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of the

peak spurious spectral component. The peak spurious compo-

nent may or may not be a harmonic. May be reported in dBc

(i.e., degrades as signal level is lowered), or in dBFS (always

related back to converter full scale).

Two-Tone Intermodulation Distortion Rejection

The ratio of the rms value of either input tone to the rms value

of the worst third order intermodulation product; reported in dBc.

tPD

AIN

ENCODE

D11–D0

SAMPLE N–1

SAMPLE N

SAMPLE N+10

SAMPLE N+11

SAMPLE N+9

SAMPLE N+1

tEH

tEL

1/fS

DATA N–11

DATA N–10

N–9

DATA N–1

DATA N

DATA N + 1

N–2

Figure 1. Timing Diagram

VCC

VREFIN

Figure 2. Equivalent Voltage Reference Input Circuit

VCC

VREFOUT

NPN

VREF OUTPUT

Figure 3. Equivalent Voltage Reference Output Circuit

Two-Tone SFDR

The ratio of the rms value of either input tone to the rms value

of the peak spurious component. The peak spurious component

may or may not be an IMD product. May be reported in dBc

(i.e., degrades as signal level is lowered), or in dBFS (always

related back to converter full scale).

Worst Harmonic

The ratio of the rms signal amplitude to the rms value of the

worst harmonic component, reported in dBc.

VCC

17k

100

17k

ENCODE

Figure 4. Equivalent Encode Input Circuit

VDD

DIGITAL

OUTPUT

DIGITAL OUTPUT

Figure 5. Equivalent Digital Output Circuit

VCC

AIN

ANALOG INPUT

Figure 6. Equivalent Analog Input Circuit

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