AD9300

–5–

REV. A

THEORY OF OPERATION

Refer to the functional block diagram of the AD9300.

As shown in the drawing, this diagram is based on the pinouts of

the DIP packaging of the models AD9300KQ and AD9300TQ.

The AD9300KP and AD9300TE are packaged in 20-pin surface

mount packages. The extra pins are used for ground connections;

the theory of operation remains the same.

The AD9300 Video Multiplexer allows the user to connect any

device and to switch between channels at megahertz rates.

The input channel, which is connected to the output is deter-

lected input will not appear at the output unless a digital “1” is

also applied to the ENABLE input pin; unless the output is

enabled, it is a high impedance. Necessary combinations to ac-

complish channel selection are shown in the Logic Truth Table.

Figure 1. Input and Output Equivalent Circuits

Bipolar construction used in the AD9300 ensures that the input

impedance of the device remains high and will not vary with

power supply voltages. This characteristic makes the AD9300,

in effect, a switchable-input buffer. An onboard bias network

makes the performance of the AD9300 independent of applied

supply voltages, which can have any nominal value from

±10 V dc to ±15 V dc.

Although the primary application for the AD9300 is the routing

of video signals, the harmonic and dynamic attributes of the

device make it appropriate for other applications. The AD9300

has exceptional performance when switching video signals and

can also be used for switching other analog signals requiring

greater dynamic range and/or precision than those in video.

As shown in Figure 1, each analog input is connected to the

base of a bipolar transistor. If Channel 1 is selected, a current

switch is closed and routes current through the input transistor

for Channel 1.

If Channel 2 is then selected by the digital inputs, the current

switch for Channel 1 is opened and the current switch for Chan-

nel 2 is closed. This causes current to be routed away from the

Channel 1 transistor and into the Channel 2 input transistor.

Whenever a channel’s input device is carrying current, the ana-

log input applied to that channel is passed to the output stage.

The operation of the output stage is similar to that of the input

stages. Whenever the output stage is enabled with a HIGH digi-

tal “1” signal at the ENABLE pin, the output transistor will

carry current and pass the selected analog input.

When the output stage is disabled (by virtue of the ENABLE

pin being driven LOW with a digital “0”), the output current

switch is opened. This routes the current to other circuits within

the AD9300 that keep the output transistor biased “off.” These

circuits require approximately 1

µA of bias current from the load

connected to the output of the multiplexer. In the absence of a

terminating load and the resulting dc bias, the output of the

AD9300 “floats” at –2.5 V.

In summary, when the AD9300 is enabled by the ENABLE pin

being driven HIGH with a digital “1,” the selected analog input

channel acts as a buffer for the input and the output of the mul-

tiplexer is a low impedance. When the AD9300 is disabled with

a digital “0” LOW signal, the selected channel acts as an open

switch for the input, and the output of the unit becomes a high

impedance. This characteristic allows the user to wire-or several

AD9300 Analog Multiplexers together to form switch matrices.