AD9241EB datasheet(19/24 Pages) AD

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AD9241

REV. 0

–19–

the A/D may contain serrations to steer currents in predictable

directions where cross-coupling between analog and digital

would otherwise be unavoidable. The AD9241/EB ground lay-

out shown in Figure 52 depicts the serrated type of arrange-

ment. The analog and digital grounds are connected by a jumper

below the A/D.

Analog and Digital Supply Decoupling

The AD9241 features separate analog and digital supply and

ground pins, helping to minimize digital corruption of sensitive

analog signals.

FREQUENCY – kHz

120

100

1000

100

DVDD

AVDD

Figure 45. PSRR vs. Frequency

Figure 45 shows the power supply rejection ratio vs. frequency

for a 200 mV p-p ripple applied to both AVDD and DVDD.

In general, AVDD, the analog supply, should be decoupled to

AVSS, the analog common, as close to the chip as physically

possible. Figure 46 shows the recommended decoupling for the

analog supplies; 0.1

µF ceramic chip capacitors should provide

adequately low impedance over a wide frequency range. Note

that the AVDD and AVSS pins are co-located on the AD9241

to simplify the layout of the decoupling capacitors and provide

the shortest possible PCB trace lengths. The AD9241/EB power

plane layout shown in Figure 53 depicts a typical arrangement

using a multilayer PCB.

0.1µF

AVDD

AVSS

AD9241

0.1µF

AVDD

AVSS

Figure 46. Analog Supply Decoupling

The CML is an internal analog bias point used internally by the

AD9241. This pin must be decoupled with at least a 0.1

µF

capacitor as shown in Figure 47. The dc level of CML is ap-

proximately AVDD/2. This voltage should be buffered if it is to

be used for any external biasing.

0.1µF

CML

AD9241

Figure 47. CML Decoupling

The digital activity on the AD9241 chip falls into two general

categories: correction logic and output drivers. The internal

correction logic draws relatively small surges of current, prima-

rily during the clock transitions. The output drivers draw large

current impulses while the output bits are changing. The size

and duration of these currents are a function of the load on the

output bits: large capacitive loads are to be avoided. Note that

the internal correction logic of the AD9241 is referenced DVDD

while the output drivers are referenced to DRVDD.

The decoupling shown in Figure 48 (a 0.1

µF ceramic chip

capacitor) is appropriate for a reasonable capacitive load on the

digital outputs (typically 20 pF on each pin). Applications in-

volving greater digital loads should consider increasing the digi-

tal decoupling proportionally and/or using external buffers/

latches.

0.1µF

DVDD

DVSS

AD9241

DRVDD

DRVSS

0.1µF

Figure 48. Digital Supply Decoupling

A complete decoupling scheme will also include large tantalum

or electrolytic capacitors on the PCB to reduce low-frequency

ripple to negligible levels. Refer to the AD9241/EB schematic

and layouts in Figures 49–53 for more information regarding the

placement of decoupling capacitors.

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