AD9200ARSRL datasheet(13/24 Pages) AD

13 / 24 page

AD9200

–13–

REV. E

The input capacitor should be sized to allow sufficient acquisi-

tion time of the clamp voltage at AIN within the CLAMP inter-

val, but also be sized to minimize droop between clamping

intervals. Specifically, the acquisition time when the switch is

closed will equal:

T ACQ = RINCIN ln









where VC is the voltage change required across CIN, and VE is

the error voltage. VC is calculated by taking the difference be-

tween the initial input dc level at the start of the clamp interval

and the clamp voltage supplied at CLAMPIN. VE is a system-

dependent parameter, and equals the maximum tolerable devia-

tion from VC. For example, if a 2-volt input level needs to be

clamped to 1 volt at the AD9200’s input within 10 millivolts,

then VC equals 2 – 1 or 1 volt, and VE equals 10 mV. Note that

once the proper clamp level is attained at the input, only a very

small voltage change will be required to correct for droop.

The voltage droop is calculated with the following equation:

IBIAS

CIN

()

where t = time between clamping intervals.

The bias current of the AD9200 will depend on the sampling

rate, FS. The switched capacitor input AIN appears resistive

over time, with an input resistance equal to 1/CSFS. Given a

sampling rate of 20 MSPS and an input capacitance of 1 pF, the

input resistance is 50 k

Ω. This input resistance is equivalently

terminated at the midscale voltage of the input range. The worst

case bias current will thus result when the input signal is at the

extremes of the input range, that is, the furthest distance from

the midscale voltage level. For a 1-volt input range, the maxi-

mum bias current will be

±0.5 volts divided by 50 kΩ, which is

±10 µA.

If droop is a critical parameter, then the minimum value of CIN

should be calculated first based on the droop requirement.

Acquisition time—the width of the CLAMP pulse—can be

adjusted accordingly once the minimum capacitor value is cho-

sen. A tradeoff will often need to be made between droop and

acquisition time, or error voltage VE.

Clamp Circuit Example

A single supply video amplifier outputs a level-shifted video

signal between 2 and 3 volts with the following parameters:

horizontal period = 63.56

µs,

horizontal sync interval = 10.9

µs,

horizontal sync pulse = 4.7

µs,

sync amplitude = 0.3 volts,

video amplitude of 0.7 volts,

reference black level = 2.3 volts

The video signal must be dc restored from a 2- to 3-volt range

down to a 1- to 2-volt range. Configuring the AD9200 for a

one volt input span with an input range from 1 to 2 volts (see

Figure 24), the CLAMPIN voltage can be set to 1 volt with an

external voltage or by direct connection to REFBS. The CLAMP

pulse may be applied during the SYNC pulse, or during the

back porch to truncate the SYNC below the AD9200’s mini-

mum input voltage. With a CIN = 1

µF, and R

IN = 20

Ω, the

acquisition time needed to set the input dc level to one volt

with 1 mV accuracy is about 140

µs, assuming a full 1 volt V

With a 1

µF input coupling capacitor, the droop across one

horizontal can be calculated:

IBIAS = 10

µA, and t = 63.5 µs, so dV = 0.635 mV, which is less

than one LSB.

After the input capacitor is initially charged, the clamp pulse-

width only needs to be wide enough to correct small voltage

errors such as the droop. The fine scale settling characteristics

of the clamp circuitry are shown in Table II.

Depending on the required accuracy, a CLAMP pulsewidth of

µs–3 µs should work in most applications. The OFFSET val-

ues ignore the contribution of offset from the clamp amplifier;

they simply compare the output code with a “final value” mea-

sured with a much longer CLAMP pulse duration.

Table II.

CLAMP

OFFSET

µs

<1 LSB

µs

5 LSBs

µs

7 LSBs

µs

11 LSBs

µs

19 LSBs

µs

42 LSBs

CLAMP IN

AD9200

CLAMP

AIN

CIN

RIN

SHA

SW1

Figure 24a. Clamp Operation

0.1 F

10 F

AIN

REFTF

REFBS

MODE

AD9200

REFTS

0.1 F

REFBF

CLAMP

CLAMPIN

AVDD

SHORT TO REFBS

OR EXTERNAL DC

0.1 F

Figure 24b. Video Clamp Circuit

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