REV. 0

AD8381

–12–

Operating Modes—Six-Channel Systems

The simplest full color LCD-based system is characterized by an

image processor with a single 10-bit-wide data bus and a 6-channel

LCD per color.

Such systems usually have VGA or SVGA resolution and require a

single AD8381 per color.

The INV input facilitates column and row inversion for

these systems.

–6

0

6

VID0

–5

1

7

VID1

–4

2

8

VID2

–3

3

9

VID3

–2

4

10

VID4

–1

5

11

VID5

CLK

STSQ

XFR

01

2

3

45

6

7

8

9

10

–1

11

12

DB(0:9)

CH 0

CH 1

CH 2

CH 3

CH 4

CH 5

0

6

12

1

7

2

8

3

9

4

10

–1

5

11

Figure 7. Six-Channel System Timing Diagram, E/O = H,

R/L = LOW

Operating Modes—12-Channel Systems

Single and dual data bus type 12-channel systems are com-

monly in use.

The single data bus 12-channel system is characterized by an

image processor with a single, 10-bit data bus and a 12-channel

LCD per color. The maximum resolution of such a system is

usually up to 85 Hz XGA or 75 Hz SXGA and requires two

AD8381s per color.

One AD8381 is set to run in EVEN mode while the other is in

ODD mode. Both AD8381s share the same data bus and CLK.

The timing diagram of such a system is shown in Figure 8.

The dual data bus 12-channel system is characterized by an

image processor with two 10-bit parallel data buses and a

12-channel LCD. The maximum resolution of such a system

is usually up to 75 Hz UXGA and requires two AD8381s per color.

Both AD8381s may be set to run in EVEN mode and may share

the same CLK. The timing diagram of each AD8381 in such

a system is identical to that of the 6-channel system.

The INV input facilitates column, row, and pixel inversion for

both types of 12-channel systems.

0

2

4

6

8

10

12

14

16

18

20

22

–2

0

2

4

6

8

10

12

14

18

20

22

CH0

CH1

CH2

CH3

CH4

CH5

VID0

VID1

VID2

VID3

VID4

VID5

16

1

3

5

7

9

11

13

15

17

19

21

23

1

3

5

7

9

11

CH0

CH1

CH2

CH3

CH4

CH5

VID0

VID1

VID2

VID3

VID4

VID5

13

15

17

19

21

23

–3

STSQ

EVEN

STSQ

ODD

XFR

R/L

E/O

EVEN

E/O

ODD

PIXEL CLK

–3 –2

12345

6

7

8

9 10

12 13 14 15 16 17 18 19 20 21 22 23 24

DB (0:9)

CLK

0

–1

–12

–10

–8

–6

–4

–2

–1

–11

–9

–7

–5

–3

–1

11

Figure 8. Twelve-Channel Even/Odd System Timing

Diagram

Operating Modes—Large Channel Count Systems

To facilitate 18, 24, or higher channel systems, any number of

required AD8381s may be cascaded.