AD831

REV. B

–7–

THEORY OF OPERATION

The AD831 consists of a mixer core, a limiting amplifier, a low

noise output amplifier, and a bias circuit (Figure 17).

The mixer’s RF input is converted into differential currents by a

highly linear, Class A voltage-to-current converter, formed by

transistors Q1, Q2 and resistors R1, R2. The resulting currents

drive the differential pairs Q3, Q4 and Q5, Q6. The LO input is

through a high gain, low noise limiting amplifier that converts

the –10 dBm LO input into a square wave. This square wave

drives the differential pairs Q3, Q4 and Q5, Q6 and produces a

high level output at IFP and IFN—consisting of the sum and

difference frequencies of the RF and LO inputs—and a series of

lower level outputs caused by odd harmonics of the LO fre-

quency mixing with the RF input.

An on-chip network supplies the bias current to the RF and LO

inputs when these are ac coupled; this network is disabled when

the AD831 is dc coupled.

When the integral output amplifier is used, pins IFN and IFP

are connected directly to pins AFN and AFP; the on-chip load

resistors convert the output current into a voltage that drives the

output amplifier. The ratio of these load resistors to resistors

R1, R2 provides nominal unity gain (0 dB) from RF to IF. The

expression for the gain, in decibels, is

4

π









1

2









π

2









Equation 1

where

4

π

is the amplitude of the fundamental component of a square wave

1

2

is the conversion loss

π

2

is the small signal dc gain of the AD831 when the LO input

is driven fully positive or negative.

20

2

Q3

R5

1k

Ω

LIMITING

AMPLIFIER

16

17

CURRENT

MIRROR

VP

50

Ω

50

Ω

20

Ω

20

Ω

BIAS

18mA TYP

IFN

AN

AP

IFP

19

3

18mA TYP

5k

Ω

5k

Ω

Q1

Q2

Q5

Q6

Q4

R4

1k

Ω

R1

20

Ω

R2

20

Ω

R3

26

Ω

Q7

BIAS

36

Ω

50

Ω

50

Ω

18

OUT

VFB

COM

12mA TYP

36mA TYP

27mA TYP

LOP

LON

RFP

RFN

VP

BIAS

VN

LOCAL

OSCILLATOR

INPUT

RF

INPUT

1

10

11

6

7

BIAS

CURRENT

Figure 17. Simplified Schematic Diagram