AD8115AST datasheet(16/26 Pages) AD

16 / 26 page

AD8114/AD8115

–16–

REV. 0

APPLIED. Programming the full shift register one time to a

desired state, either by serial or parallel programming after

initial power-up, will eliminate the possibility of programming

the matrix to an unknown state.

To change an output’s programming via parallel programming,

SER/PAR and UPDATE should be taken HIGH and CE should

be taken LOW. The CLK signal should be in the HIGH state.

The 4-bit address of the output to be programmed should be put

on A0–A3. The first four data bits (D0–D3) should contain the

information that identifies the input that gets programmed to the

output that is addressed. The fourth data bit (D4) will deter-

mine the enabled state of the output. If D4 is LOW (output

disabled) then the data on D0–D3 does not matter.

After the desired address and data signals have been established,

they can be latched into the shift register by a HIGH to LOW

transition of the CLK signal. The matrix will not be programmed,

however, until the UPDATE signal is taken low. It is thus pos-

sible to latch in new data for several or all of the outputs first via

successive negative transitions of CLK while UPDATE is held

high, and then have all the new data take effect when UPDATE

goes LOW. This is the technique that should be used when

programming the device for the first time after power-up when

using parallel programming.

POWER-ON RESET

When powering up the AD8114/AD8115 it is usually desirable

to have the outputs come up in the disabled state. The RESET

pin, when taken LOW will cause all outputs to be in the dis-

abled state. However, the RESET signal DOES NOT RESET

ALL REGISTERS in the AD8114/AD8115 This is important

when operating in the parallel programming mode. Please refer

to that section for information about programming internal

registers after power-up. Serial programming will program the

entire matrix each time, so no special considerations apply.

Since the data in the shift register is random after power-up,

they should not be used to program the matrix or else the matrix

can enter unknown states. To prevent this, DO NOT APPLY

LOGIC LOW SIGNALS TO BOTH CE AND UPDATE

INITIALLY AFTER POWER-UP. The shift register should

first be loaded with the desired data, and then UPDATE can be

taken LOW to program the device.

The RESET pin has a 20 k

Ω pull-up resistor to DVDD that can

be used to create a simple power-up reset circuit. A capacitor

from RESET to ground will hold RESET LOW for some time

while the rest of the device stabilizes. The LOW condition will

cause all the outputs to be disabled. The capacitor will then

charge through the pull-up resistor to the HIGH state, thus

allowing full programming capability of the device.

GAIN SELECTION

The 16

× 16 crosspoints come in two versions, depending on the

gain of the analog circuit paths that is desired. The AD8114

device is unity gain and can be used for analog logic switching

and other applications where unity gain is desired. The AD8114

can also be used for the input and interior sections of larger

crosspoint arrays where termination of output signals is not

usually used. The AD8114 outputs have a very high impedance

when their outputs are disabled.

The AD8115 can be used for devices that will be used to drive

a terminated cable with its outputs. This device has a built-in

gain-of-two that eliminates the need for a gain-of-two buffer to

drive a video line. Its high output disabled impedance minimizes

signal degradation when paralleling additional outputs.

CREATING LARGER CROSSPOINT ARRAYS

The AD8114/AD8115 are high density building blocks for cre-

ating crosspoint arrays of dimensions larger than 16

× 16. Vari-

ous features, such as output disable, chip enable, and gain-

of-one and gain-of-two options, are useful for creating larger

arrays. When required for customizing a crosspoint array size,

they can be used with the AD8108 and AD8109, a pair (unity

gain and gain-of-two) of 8

× 8 video crosspoint switches, or the

AD8110 and AD8111, a pair (unity gain and gain-of-two)

× 8 video crosspoint switches.

The first consideration in constructing a larger crosspoint is to

determine the minimum number of devices are required. The

× 16 architecture of the AD8114/AD8115 contains 256

“points,” which is a factor of 64 greater than a 4

× 1 crosspoint

(or multiplexer). The PC board area, power consumption and

design effort savings are readily apparent when compared to

using these smaller devices.

For a nonblocking crosspoint, the number of points required is

the product of the number of inputs multiplied by the number

of outputs. Nonblocking requires that the programming of a

given input to one or more outputs does not restrict the avail-

ability of that input to be a source for any other outputs.

Some nonblocking crosspoint architectures will require more

than this minimum as calculated above. Also, there are blocking

architectures that can be constructed with fewer devices than

this minimum. These systems have connectivity available on a

statistical basis that is determined when designing the overall

system.

The basic concept in constructing larger crosspoint arrays is

to connect inputs in parallel in a horizontal direction and to

“wire-OR” the outputs together in the vertical direction. The

meaning of horizontal and vertical can best be understood by

looking at a diagram. Figure 42 illustrates this concept for a

× 32 crosspoint array that uses four AD8114s or AD8115s.

AD8114

AD8115

AD8114

AD8115

RTERM

IN 00–15

RTERM

IN 16–31

AD8114

AD8115

AD8114

AD8115

Figure 42. 32

× 32 Crosspoint Array Using Four AD8114s

or Four AD8115s

The inputs are each uniquely assigned to each of the 32 inputs

of the two devices and terminated appropriately. The outputs

are wired-ORed together in pairs. The output from only one of

a wire-ORed pair should be enabled at any given time. The

device programming software must be properly written to cause

this to happen.

Using additional crosspoint devices in the design can lower the

number of outputs that have to be wire-ORed together. Figure

43 shows a block diagram of a system using eight AD8114s and

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