AD7887ARM datasheet(4/16 Pages) AD

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REV. B

AD7887

–4–

Limit at TMIN, TMAX

(A, B Versions)

Parameter

+4.75 V to +5.25 V

+2.7 V to +3.6 V

Units

Description

fSCLK

MHz max

tCONVERT

14.5 tSCLK

tACQ

1.5 tSCLK

Throughput Time = tCONVERT + tACQ = 16 tSCLK

ns min

CS to SCLK Setup Time

ns max

Delay from CS Until DOUT Three-State Disabled

100

ns max

Data Access Time after SCLK Falling Edge

ns min

Data Setup Time Prior to SCLK Rising Edge

ns min

Data Valid to SCLK Hold Time

0.4 tSCLK

ns min

SCLK High Pulsewidth

0.4 tSCLK

ns min

SCLK Low Pulsewidth

ns max

CS Rising Edge to DOUT High Impedance

µs typ

Power-Up Time from Shutdown

NOTES

1Sample tested at +25

°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V

DD) and timed from a voltage level of 1.6 volts.

2Mark/Space ratio for the SCLK input is 40/60 to 60/40.

3Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.

8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number i s then extrapolated back

to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of

the part and is independent of the bus loading.

Specifications subject to change without notice.

TIMING SPECIFICATIONS1

+1.6V

IOL

200 A

IOH

OUTPUT

50pF

Figure 1. Load Circuit for Digital Output Timing Specifications

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