AD7851AR datasheet(21/36 Pages) AD

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REV. A

AD7851

SYSTEM OFFSET

CALIBRATION

SYS OFFSET

VREF – 1LSB

AGND

MAX SYSTEM OFFSET

±5% OF V

REF

MAX SYSTEM FULL SCALE

±2.5% FROM V

REF

ANALOG

INPUT

RANGE

VREF – 1LSB

ANALOG

INPUT

RANGE

SYS OFFSET

AGND

MAX SYSTEM OFFSET

±5% OF V

REF

VREF + SYS OFFSET

Figure 28. System Offset Calibration

Figure 29 shows a system gain calibration (assuming a system

full scale greater than the reference voltage) where the analog

input range has been increased after the system gain calibration

is completed. A system full-scale voltage less than the reference

voltage may also be accounted for a by a system gain calibration.

SYSTEM GAIN

CALIBRATION

VREF – 1LSB

AGND

MAX SYSTEM FULL SCALE

±2.5% FROM V

REF

ANALOG

INPUT

RANGE

VREF – 1LSB

ANALOG

INPUT

RANGE

AGND

SYS FULL S.

MAX SYSTEM FULL SCALE

±2.5% FROM V

REF

Figure 29. System Gain Calibration

Finally in Figure 30 both the system offset and gain are accounted

for by the system offset followed by a system gain calibration.

First the analog input range is shifted upwards by the positive

system offset and then the analog input range is adjusted at the

top end to account for the system full scale.

SYSTEM OFFSET

CALIBRATION

FOLLOWED BY

SYSTEM GAIN

CALIBRATION

SYS OFFSET

VREF – 1LSB

AGND

MAX SYSTEM OFFSET

±5% OF V

REF

MAX SYSTEM FULL SCALE

±2.5% FROM V

REF

ANALOG

INPUT

RANGE

VREF – 1LSB

ANALOG

INPUT

RANGE

SYS OFFSET

AGND

MAX SYSTEM OFFSET

±5% OF V

REF

VREF + SYS OFFSET

SYS F.S.

MAX SYSTEM FULL SCALE

±2.5% FROM V

REF

SYS F.S.

Figure 30. System (Gain + Offset) Calibration

Self-Calibration Timing

The diagram of Figure 27 shows the timing for a full self-

calibration. Here the BUSY line stays high for the full length of

the self-calibration. A self-calibration is initiated by bringing the

CAL

pin low (which initiates an internal reset) and then high

again or by writing to the control register and setting the

STCAL bit to 1 (note that if the part is in a power-down mode, the

CAL

pulse width must take account of the power-up time). The

BUSY line is triggered high from the rising edge of CAL (or the

end of the write to the control register if calibration is initiated

in software), and BUSY will go low when the full self-calibration

is complete after a time tCAL as shown in Figure 27.

t1 = 100ns MIN,

t15 = 2.5 tCLKIN MAX,

tCAL = 250026 tCLKIN

CAL (I/P)

BUSY (O/P)

t15

tCAL

Figure 27. Timing Diagram for Full Self-Calibration

For the self-(gain + offset), self-offset and self-gain calibrations,

the BUSY line will be triggered high by the rising edge of the

CAL

signal (or the end of the write to the control register if cali-

bration is initiated in software) and will stay high for the full du-

ration of the self-calibration. The length of time that the BUSY

is high for will depend on the type of self-calibration that is initi-

ated. Typical figures are given in Table IX. The timing dia-

grams for the other self-calibration options will be similar to that

outlined in Figure 27.

System Calibration Description

System calibration allows the user to take out system errors

external to the AD7851 as well as calibrate the errors of the

AD7851 itself. The maximum calibration range for the system

offset errors is

±5% of V

REF and for the system gain errors is

±2.5% of V

REF. This means that the maximum allowable system

offset voltage applied between the AIN(+) and AIN(–) pins for

the calibration to adjust out this error is

±0.05 × V

REF (i.e., the

AIN(+) can be 0.05

× V

REF above AIN(–) or 0.05 × VREF below

AIN(–)). For the system gain error the maximum allowable

system full-scale voltage, in unipolar mode, that can be applied

between AIN(+) and AIN(–) for the calibration to adjust out

this error is VREF

± 0.025 × V

REF (i.e., the AIN(+) can be VREF +

0.025

× V

REF above AIN(–) or VREF – 0.025

× V

REF above

AIN(–)). If the system offset or system gain errors are outside

the ranges mentioned, the system calibration algorithm will

reduce the errors as much as the trim range allows.

Figures 28 through 30 illustrate why a specific type of system

calibration might be used. Figure 29 shows a system offset cali-

bration (assuming a positive offset) where the analog input

range has been shifted upwards by the system offset after the

system offset calibration is completed. A negative offset may

also be accounted for by a system offset calibration.

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