AD7836AS datasheet(8/12 Pages) AD

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AD7836

–8–

REV. A

Unipolar Configuration

Figure 11 shows the AD7836 in the unipolar binary circuit con-

figuration. The VREF(+) input of the DAC is driven by the

AD586, a +5 V reference. VREF(–) is tied to ground. Table II

gives the code table for unipolar operation of the AD7836.

Other suitable references include the REF02, a precision 5 V

reference, and the REF195, a low dropout, micropower preci-

sion +5 V reference.

*ADDITIONAL PINS OMITTED FOR CLARITY

+15V

+5V

VOUT

(0 TO +10V)

VCC

SIGNAL

GND

1nF

AGND

DGND

VDD

VOUT

VREF(+)

VREF(–)

VSS

–15V

10k

AD7836

AD586

SIGNAL

GND

DUTGND

Figure 11. Unipolar +5 V Operation

Offset and gain may be adjusted in Figure 2 as follows: To ad-

just offset, disconnect the VREF(–) input from 0 V, load the DAC

with all 0s and adjust the VREF(–) voltage until VOUT = 0 V. For

gain adjustment, the AD7836 should be loaded with all 1s and

R1 adjusted until VOUT = 10 V(16383/16384) = 9.999389.

Many circuits will not require these offset and gain adjustments. In

these circuits R1 can be omitted. Pin 5 of the AD586 may be left

open circuit and Pin 2 (VREF(–)) of the AD7836 tied to 0 V.

Table II. Code Table for Unipolar Operation

Binary Number in DAC Latch

Analog Output

MSB

LSB

(VOUT)

1111

2 VREF (16383/16384) V

0000

2 VREF (8192/16384) V

1111

2 VREF (8191/16384) V

0000

0001

2 VREF (1/16384) V

0000

0 V

NOTE

VREF = VREF(+); VREF(–) = 0 V for unipolar operation.

For VREF(+) = +5 V, 1 LSB = +10 V/2

14 = +10 V/16384 = 610

µV.

Bipolar Configuration

Figure 12 shows the AD7836 set up for

±10 V operation. The

AD588 provides precision

±5 V tracking outputs that are fed to

the VREF(+) and VREF(–) inputs of the AD7836. The code table

for bipolar operation of the AD7836 is shown in Table III.

In Figure 12, full-scale and bipolar zero adjustments are pro-

vided by varying the gain and balance on the AD588. R2 varies

the gain on the AD588 while R3 adjusts the offset of both the

+5 V and –5 V outputs together with respect to ground.

For bipolar-zero adjustment, the DAC is loaded with

1000 . . . 0000 and R3 is adjusted until VOUT = 0 V. Full scale

is adjusted by loading the DAC with all 1s and adjusting R2 un-

til VOUT = 10(8191/8192) V = 9.998779 V.

When bipolar-zero and full-scale adjustment are not needed,

R2 and R3 can be omitted. Pin 12 on the AD588 should be

connected to Pin 11 and Pin 5 should be left floating.

*ADDITIONAL PINS OMITTED FOR CLARITY

+15V

+5V

VOUT

(–10V TO +10V)

VCC

AGND

DGND

VDD

VOUT

VREF(+)

VREF(–)

VSS

–15V

AD7836

SIGNAL

GND

DUTGND

1 F

100k

12 8 13

100k

39k

AD588

Figure 12. Bipolar

±5 V Operation

Table III. Code Table for Bipolar Operation

Binary Number in DAC Latch

Analog Output

MSB

LSB

(VOUT)

1111

2[VREF(–) + VREF (16383/16384)] V

0000

0001

2[VREF(–) + VREF (8193/16384)] V

0000

2[VREF(–) + VREF (8192/16384)] V

1111

2[VREF(–) + VREF (8191/16384)] V

0000

0001

2[VREF(–) + VREF (1/16384)] V

0000

2[VREF(–)] V

NOTE

VREF = (VREF(+) – VREF(–)).

For VREF(+) = +5 V, and VREF(–) = –5 V, VREF =10 V, 1 LSB = 2 VREF V/2

= 20 V/16384 = 1220

µV.

CONTROLLED POWER-ON OF THE OUTPUT STAGE

A block diagram of the output stage of the AD7836 is shown in

Figure 13. It is capable of driving a load of 5 k

Ω in parallel

with 50 pF. G1 to G6 are transmission gates that are used to

control the power on voltage present at VOUT. On power up G1

and G2 are also used in conjunction with the CLR input to set

VOUT to the user defined voltage present at the DUTGND pin.

When CLR is taken back high the DAC outputs reflect the data

in the DAC registers.

DAC

VOUT

DUTGND

R = 13.5k

Figure 13. Block Diagram of AD7836 Output Stage

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