AD7776/AD7777/AD7778

–6–

REV. 0

CR6: Determines whether operation is on a single channel or

simultaneous sampling on two channels. Location CR6 is a

“don’t care” for the AD7776.

CR6

Function

0

Single channel operation. Channel select

address is contained in locations CR0–CR2.

1

Two channels simultaneously sampled

and sequentially converted. Channel

select addresses contained in locations

CR0–CR2 and CR3–CR5.

CR7: Determines whether the device is in the normal operating

mode or in the half-scale test mode.

CR7

Function

0

Normal Operating Mode

1

Half-Scale Test Mode

In the half-scale test mode REFIN is internally connected as an

analog input(s). In this mode locations CR0–CR2 and CR3–

CR5 are all “don’t cares” since it is REFIN which will be con-

verted. For the AD7777 and AD7778, the contents of location

CR6 still determine whether a single or a double conversion is

carried out on the REFIN level.

CR8: Determines whether the device is in the normal operating

mode or in the powerdown mode.

CR8

Function

0

Normal Operating Mode

1

Powerdown Mode

In the powerdown mode all linear circuitry is turned off and the

REFOUT output is weakly (5 k

Ω) pulled to AGND. The input

impedance of the analog inputs and of the REFIN input re-

mains the same in either normal mode or powerdown mode. See

under Circuit Description—Powerdown Mode.

CR9: Determines whether

BUSY/INT output flag goes low and

remains low during conversion(s) or else goes low and remains

low after the conversion(s) is (are) complete.

CR9

BUSY/INT Functionality

0

Output goes low and remains low during

conversion(s).

1

Output goes low and remains low after conversion(s)

is (are) complete.

ADC Conversion Start Timing

Figure 6 shows the operating waveforms for the start of a con-

version cycle. On the rising edge of

WR, the conversion cycle

starts with the acquisition and tracking of the selected ADC

cally) after the first rising edge of CLKIN following four com-

falling edge of CLKIN as shown will be seen as the first falling

be recognized will not occur until one cycle later.

Following the “hold” on the analog input(s), two complete

CLKIN cycles are allowed for settling purposes before the MSB

decision is made. The actual decision point occurs approximately

40 ns after the rising edge of CLKIN as shown in Figure 6. A

further two CLKIN cycles are allowed for the second MSB

decision. The succeeding bit decisions are made approximately

40 ns after each rising edge of CLKIN until the conversion is

complete. At the end of conversion, if a single conversion

has been requested (CR6 = 0), the

BUSY/INT line changes

CONTROL REGISTER

The control register is 10-bits wide and can only be written to.

On power-on, all locations in the control register are automati-

cally loaded with 0s. For the single channel AD7776, locations

CR0 to CR6 of the control register are “don’t cares.” For the

quad channel AD7777, locations CR2 and CR5 are “don’t

cares.” Individual bit functions are described below.

CR0–CR2: Channel Address Locations. Determines which channel

will be selected and converted for single channel operation. For si-

multaneous sampling operation CR0–CR2 holds the address of one

of the two channels to be sampled.

AD7776

CR2 CR1

CR0

Function

X*

X

X

*X = Don’t Care

AD7777

CR2 CR1

CR0

Function

X*

0

0

X

0

1

X

1

0

X

1

1

*X = Don’t Care

AD7778

CR2 CR1

CR0

Function

0

0

0

0

0

1

0

1

0

0

1

1

1

0

0

1

0

1

1

1

0

1

1

1

CR3–CR5: Channel Address Locations. Only applicable for simul-

taneous sampling with the AD7777 or AD7778 when CR3–CR5

holds the address of the second channel to be sampled.

AD7777

CR5 CR4

CR3

Function

X*

0

0

X

0

1

X

1

0

X

1

1

*X = Don’t Care

AD7778

CR5 CR4

CR3

Function

0

0

0

0

0

1

0

1

0

0

1

1

1

0

0

1

0

1

1

1

0

1

1

1