AD7769

–12–

REV. A

Conversion is initiated on the selected AD7769 ADC channel

using a single I/O instruction, <OUT ADC, A>. The processor

then polls

INT until it goes low before reading the conversion

result using an <IN A, ADC> instruction. Writing data to the rel-

evant AD7769 DAC consists of an <OUT DAC, A> instruction.

AD7769–ADSP-2101 Interface

Figure 19 shows a typical interface to the DSP microcomputer,

the ADSP-2101. The ADSP-2101 is optimized for high speed

numeric processing tasks.

Figure 19. AD7769 to ADSP-2101 Interface

Because the instruction cycle of the ADSP-2101 is very fast

(80 ns cycle), the

WR and RD pulses must be stretched out to

suit the AD7769. This is easily achieved as the ADSP-2101

memory interface supports slower memories and memory-

mapped peripherals (i.e., AD7769) with a programmable wait

state generation capability. A number of wait states, from 0 to 7,

can be specified for each memory interface. One wait state is

sufficient for the interface to the AD7769.

AD7769–8051 Interface

A choice of two interface modes are available to the 8051

microcomputer.

Figure 20 shows a typical interface to the 8051 processor bus. It

is suitable for the maximum 8051 clock frequency of 12 MHz.

In this interface mode, Port 0 provides the multiplexed low or-

der address and data bus and Port 2 provides the high order ad-

Figure 21 shows the AD7769 interfaced to the 8051 parallel I/O

ports. This interface circuit is simpler to implement than the

previous interface to the processor bus, but, in general, the

maximum data throughput rate is much slower (for the same

clock frequencies). In addition to its simplicity, the interface to

the parallel I/O ports versus the processor bus allows indepen-

dent control of both the

WR and RD inputs to the AD7769.

For example, the 8051 can set both

WR and RD low at the

same time. This permits data from the last ADC conversion to

be written directly from the ADC register into the selected DAC

register (see Logic Truth Table). This allows very fast transfer

of data from the ADC to the DAC and is a useful feature for

some applications such as a fast, programmable, infinite sample-

and-hold function.

Figure 20. AD7769 to 8051 (Processor Bus) Interface

Figure 21. AD7769 to 8051 (Parallel l/O Ports) Interface

AD7769–MC68HC11 Interface

Figure 22 shows a typical interface between the AD7769 and the

MC68HC11 microcomputer. This interface is designed for the

maximum MC68HC11 clock speed of 8.4 MHz. The microcom-

puter is operated in the expanded multiplexed mode, with the

AD7769 as a memory mapped peripheral. The expansion bus is

made up of Ports B and C, and control signals AS and R/

W.

Figure 22. AD7769 to MC68HC11 Interfaced