AD7729

–4–

REV. 0

TIMING CHARACTERISTICS

Limit at

Parameter

Units

Description

AUXILIARY FUNCTIONS

Clock Signals

See Figure 2.

76

ns min

MCLK Period

30.4

ns min

MCLK Width Low

30.4

ns min

MCLK Width High

ns min

ASCLK Period. See Figures 4 and 6.

0.4

× t

1

ns min

ASCLK Width Low

0.4

× t

1

ns min

ASCLK Width High

20

ns min

ASDI/ASDIFS Setup Before ASCLK Low

10

ns min

ASDI/ASDIFS Hold After ASCLK Low

15

ns max

ASDOFS Delay from ASCLK High

0

ns min

ASDOFS Hold After ASCLK High

0

ns min

ASDO Hold After ASCLK High

15

ns max

ASDO Delay from ASCLK High

10

ns min

ASDIFS Low to ASDI LSB Read by ASPORT

ns min

Interval Between Consecutive ASDIFS Pulses

Receive Section

Clock Signals

See Figures 5 and 7.

ns min

BSCLK Period

0.4

× t

1

ns min

BSCLK Width Low

0.4

× t

1

ns min

BSCLK Width High

20

ns min

BSDI/BSDIFS Setup Before BSCLK Low

10

ns min

BSDI/BSDIFS HoldAfter BSCLK Low

15

ns max

BSDOFS Delay from BSCLK High

0

ns min

BSDOFS Hold After BSCLK High

0

ns min

BSDO Hold After BSCLK High

15

ns max

BSDO Delay from BSCLK High

10

ns min

BSDIFS Low to ASDI LSB Read by BSPORT

ns min

Interval Between Consecutive BSDIFS Pulses

ASCLK = MCLK/(2

× ASCLKRATE). ASCLKRATE can have a value from 0 . . . 1023. When ASCLKRATE = 0, ASCLK = 13 MHz.

BSCLK = MCLK/(2

× BSCLKRATE). BSCLKRATE can have a value from 0 . . . 1023. When BSCLKRATE = 0, BSCLK = 13 MHz.

Specifications subject to change without notice.

(AVDD1 = AVDD2 = +3 V

10%; DVDD1 = DVDD2 = +3 V

10%; AGND = DGND = 0 V;

Table II. Receive Section Signal Ranges

Baseband Section

Signal Range

1.3 V

± 5%

1.3 V

± 10%

ADC

ADC Signal Range

Differential Input

Single-Ended Input

Signal Range

Differential

± V

Single-Ended

± V

REFCAP

Table III. Auxiliary Section Signal Ranges

AUXDAC

Signal Range

Output Code

Code 000

2/32

× V

REFCAP

Code 3FF