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AD7716 датащи(PDF) 3 Page - Analog Devices

номер детали AD7716
подробное описание детали  LC2MOS 22-Bit Data Acquisition System
PDF  16 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD7716 датащи(HTML) 3 Page - Analog Devices

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REV. A
–3–
AD7716
Table I. Typical Usable Dynamic Range, RMS Noise and Filter Settling Time vs. Filter Cutoff Frequency
Programmed Cutoff
Output Update
Usable Dynamic
RMS Noise
Filter Settling Time to
Absolute Group
N
Frequency (Hz)
Rate (Hz)
Range (dB)
( V)
0.0007% FS (ms)
Delay (ms)
0
584
2232
99
21
1.35
0.675
1
292
1116
102
14
2.7
1.35
2
146
558
105
10
5.4
2.7
3
73
279
108
7
10.8
5.4
4
36.5
140
111
5
21.6
10.8
NOTE
Usable Dynamic Range is defined as the ratio of the rms full-scale reading (sine wave input) to the rms noise of the converter.
CONTROL REGISTER TIMING CHARACTERISTICS1, 2 (AV
DD = DVDD = +5 V
5%; AVSS = –5 V
5%; AGND =
DGND = 0 V; fCLKIN = 8 MHz; Input Levels: Logic 0 = 0 V, Logic 1 = DVDD; unless otherwise noted)
Limit at TMIN, TMAX
Parameter
(B Version)
Units
Conditions/Comments
t1
1/fCLKIN
ns min
SCLK Period
t2
77
ns min
SCLK Width
t3
30
ns min
TFS
Setup Time
t4
20
ns min
SDATA Setup Time
t5
10
ns min
SDATA Hold Time
t6
20
ns min
TFS
Hold Time
NOTES
1Sample tested at +25
°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2See Figure 2.
3CLKIN Duty Cycle range is 40% to 60%.
200
µA
IOH
+2.1V
TO
OUTPUT
PIN
1.6mA
CL
50pF
IOL
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
DB4
(DB12)
DB3
(DB11)
DB2
(DB10)
DB1
(DB9)
DB0
(DB8)
DB5
(DB13)
DB6
(DB14)
DB7
(DB15)
t2
SCLK (I)
SDATA (I)
TFS (I)
t2
t5
t4
t3
t6
t1
Figure 2. Control Register Timing Diagram



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