AD7713 datasheet(16/28 Pages) AD

16 / 28 page

REV. C

–16–

AD7713

System Synchronization

If multiple AD7713s are operated from a common master clock,

they can be synchronized to update their output registers simul-

taneously. A falling edge on the SYNC input resets the filter

and places the AD7713 into a consistent, known state. A com-

mon signal to the AD7713s’ SYNC inputs will synchronize their

operation. This would normally be done after each AD7713 has

performed its own calibration or has had calibration coefficients

loaded to it.

The SYNC input can also be used to reset the digital filter in

systems where the turn-on time of the digital power supply

(DVDD) is very long. In such cases, the AD7713 will start oper-

ating internally before the DVDD line has reached its minimum

operating level, +4.75 V. With a low DVDD voltage, the

AD7713’s internal digital filter logic does not operate correctly.

Thus, the AD7713 may have clocked itself into an incorrect

operating condition by the time that DVDD has reached its cor-

rect level. The digital filter will be reset upon issue of a calibra-

tion command (whether it is self-calibration, system calibration

or background calibration) to the AD7713. This ensures correct

operation of the AD7713. In systems where the power-on de-

fault conditions of the AD7713 are acceptable, and no calibra-

tion is performed after power-on, issuing a SYNC pulse to the

AD7713 will reset the AD7713’s digital filter logic. An R, C on

the SYNC line, with R, C time constant longer than the DVDD

power-on time, will perform the SYNC function.

ACCURACY

Sigma-delta ADCs, like VFCs and other integrating ADCs, do

not contain any source of nonmonotonicity and inherently offer

no missing codes performance. The AD7713 achieves excellent

linearity by the use of high quality, on-chip silicon dioxide ca-

pacitors, which have a very low capacitance/voltage coefficient.

The device also achieves low input drift through the use of chopper

stabilized techniques in its input stage. To ensure excellent perfor-

mance over time and temperature, the AD7713 uses digital calibra-

tion techniques that minimize offset and gain error.

AUTOCALIBRATION

Autocalibration on the AD7713 removes offset and gain errors

from the device. A calibration routine should be initiated on the

device whenever there is a change in the ambient operating tem-

perature or supply voltage. It should also be initiated if there is a

change in the selected gain, filter notch or bipolar/unipolar input

range. However, if the AD7713 is in its background calibration

mode, the above changes are all automatically taken care of

(after the settling time of the filter has been allowed for).

The AD7713 offers self-calibration, system calibration and

background calibration facilities. For calibration to occur on the

selected channel, the on-chip microcontroller must record the

modulator output for two different input conditions. These are

“zero-scale” and “full-scale” points. With these readings, the

microcontroller can calculate the gain slope for the input to out-

put transfer function of the converter. Internally, the part works

with a resolution of 33 bits to determine its conversion result of

either 16 bits or 24 bits.

voltage can go to +5 V with no degradation in performance

provided that the absolute value of REF IN(+) and REF IN(–)

does not exceed its AVDD and AGND limits. The part is also

functional with VREF voltages down to 1 V but with degraded

performance as the output noise will, in terms of LSB size, be

larger. REF IN(+) must always be greater than REF IN(–) for

correct operation of the AD7713.

Both reference inputs provide a high impedance, dynamic load

similar to the analog inputs. The maximum dc input leakage

current is 10 pA (

±1 nA over temperature) and source resis-

tance may result in gain errors on the part. The reference inputs

look like the AIN1 analog input (see Figure 7). In this case,

RINT is 5 k

Ω typ and C

INT varies with gain. The input sample

rate is fCLK IN/256 and does not vary with gain. For gains of 1

to 8 CINT is 20 pF; for a gain of 16 it is 10 pF; for a gain of 32

it is 5 pF; for a gain of 64 it is 2.5 pF; and for a gain of 128 it is

1.25 pF.

The digital filter of the AD7713 removes noise from the refer-

ence input just as it does with the analog input, and the same

limitations apply regarding lack of noise rejection at integer mul-

tiples of the sampling frequency. The output noise performance

outlined in Tables I and II assumes a clean reference. If the ref-

erence noise in the bandwidth of interest is excessive, it can

degrade the performance of the AD7713. A recommended refer-

ence source for the AD7713 is the AD680, a 2.5 V reference.

USING THE AD7713

SYSTEM DESIGN CONSIDERATIONS

The AD7713 operates differently from successive approximation

ADCs or integrating ADCs. Since it samples the signal continu-

ously, like a tracking ADC, there is no need for a start convert

command. The output register is updated at a rate determined

by the first notch of the filter and the output can be read at any

time, either synchronously or asynchronously.

Clocking

The AD7713 requires a master clock input, which may be an

external TTL/CMOS compatible clock signal applied to the

MCLK IN pin with the MCLK OUT pin left unconnected.

Alternatively, a crystal of the correct frequency can be con-

nected between MCLK IN and MCLK OUT, in which case the

clock circuit will function as a crystal controlled oscillator. For

lower clock frequencies, a ceramic resonator may be used in-

stead of the crystal. For these lower frequency oscillators, exter-

nal capacitors may be required on either the ceramic resonator

or on the crystal.

The input sampling frequency, the modulator sampling fre-

quency, the –3 dB frequency, output update rate and calibration

time are all directly related to the master clock frequency,

fCLK IN. Reducing the master clock frequency by a factor of two

will halve the above frequencies and update rate and will double

the calibration time.

The current drawn from the DVDD power supply is also directly

related to fCLK IN. Reducing fCLK IN by a factor of two will halve

the DVDD current but will not affect the current drawn from the

AVDD power supply.

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