AD7709

–13–

REV. PrA

January 2001

PRELIMINARY TECHNICAL DATA

Status Register - (A1,A0=0,0; Power-On-Reset = 00Hex):

The ADC Status Register is an 8-bit read-only register. To access the ADC Status Register, the user must write to the

Communications Register selecting

the next operation to be a read and load bits A1-A0 with 0,0. Table V outlines the

bit designations for the Status Register. SR0 through SR7 indicate the bit location, SR denoting the bits are in

the Status Register. SR7 denotes the first bit of the data stream.

The number in brackets indicates the power-on/reset

default status of that bit.

SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

RDY(0)

0(0)

0(0)

0(0)

ERR (0)

0(0)

STBY(0)

LOCK(0)

Table V. Status Register Bit Designations

Bit

Bit

Location

Mnemonic

Description

SR7

RDY

Ready bit for the ADC

Set when data is transferred to the ADC data register.

The RDY bit is cleared automatically a period of time before the data register is updated with a

new conversion result or after the ADC data register has been read.

SR6

0

Bit is automatically cleared. Reserved for future use

SR5

0

This bit is automatically cleared. Reserved for future use

SR4

0

This bit is automatically cleared. Reserved for future use

SR3

ERR

ADC Error Bit. This qualifying bit is set at the same at the RDY bit.

When Set it indicates that the result written to the ADC data register has been clamped to all

zeros or all ones. Error sources include Overrange and loss of lock.

This bit is Cleared at the same time as the RDY bit.

SR2

0

This bit is automatically cleared. Reserved for future use

SR1

STBY

Standby bit indication.

When Set it indicates that the AD7709 is in low power mode.

Cleared when the ADC is powerd up.

SR0

LOCK

PLL lock status bit.

This bit is SET if the PLL has locked onto the 32kHz crystal oscillator clock. The ADC will

not start conversion till this bit has been set. If the LOCK bit subsequently goes low the ERR

bit will be set.

Configuration Register(CONFIG) :(A1,A0 = 0,1; Power-On-Reset = 000000Hex)

The CONFIG Register is a 24-bit register from which data can either be read or to which data can be written. This

register is used to select the input channel and configure the input range, excitation current sources and I/O port.Table

XIII outlines the bit designations for this register. CONFIG24 through CONFIG0 indicate the bit location, CONFIG

denoting the bits are in the Configuration Register. CONFIG24 denotes the first bit of the data stream. The number in

brackets indicates the power-on/reset default status of that bit. A write to the CONFIG register has immediate effect and

does not reset the the ADCs. Thus , if a current source is switched while the ADC is converting the user will have to wait

for the fullsettling time of the sinc^3 filter before getting a fully settled output. This equates to 4 outputs.