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AD7665

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DIGITAL INTERFACE

The AD7665 has a versatile digital interface; it can be interfaced

with the host system by using either a serial or parallel interface.

The serial interface is multiplexed on the parallel data bus. The

AD7665 digital interface also accommodates both 3 V or 5 V

logic by simply connecting the OVDD supply pin of the AD7665

to the host system interface digital supply. Finally, by using the

OB/

2C input pin, both two’s complement or straight binary

coding can be used.

The two signals

CS and RD control the interface. When at least

one of these signals is high, the interface outputs are in high

impedance. Usually,

CS allows the selection of each AD7665 in

multicircuits applications and is held low in a single AD7665

design.

RD is generally used to enable the conversion result on

the data bus.

t11

CNVST

BUSY

DATA

BUS

CS = RD = 0

t10

PREVIOUS CONVERSION DATA

NEW DATA

Figure 13. Master Parallel Data Timing for Reading

(Continuous Read)

PARALLEL INTERFACE

The AD7665 is configured to use the parallel interface when the

SER/

PAR is held low. The data can be read either after each

conversion, which is during the next acquisition phase, or dur-

ing the following conversion as shown, respectively, in Figure 14

and Figure 15. When the data is read during the conversion,

however, it is recommended that it be read only during the first

half of the conversion phase. That avoids any potential feed-

through between voltage transients on the digital interface and

the most critical analog conversion circuitry.

CURRENT

CONVERSION

BUSY

DATA

BUS

t12

t13

Figure 14. Slave Parallel Data Timing for Reading (Read

After Convert)

CONVERSION

t12

t13

CS = 0

CNVST,

BUSY

DATA

BUS

Figure 15. Slave Parallel Data Timing for Reading (Read

During Convert)

The BYTESWAP pin allows a glueless interface to an 8-bit bus.

As shown in Figure 16, the LSB byte is output on D[7:0] and

the MSB is output on D[15:8] when BYTESWAP is low. When

BYTESWAP is high, the LSB and MSB bytes are swapped and

the LSB is output on D[15:8] and the MSB is output on D[7:0].

By connecting BYTESWAP to an address line, the 16 data bits

can be read in 2 bytes on either D[15:8] or D[7:0].

BYTE

PINS D[15:8]

HI-Z

HIGH BYTE

LOW BYTE

HI-Z

HIGH BYTE

LOW BYTE

HI-Z

PINS D[7:0]

Figure 16. 8-Bit Parallel Interface

SERIAL INTERFACE

The AD7665 is configured to use the serial interface when the

SER/

PAR is held high. The AD7665 outputs 16 bits of data,

MSB first, on the SDOUT pin. This data is synchronized with

the 16 clock pulses provided on SCLK pin. The output data is

valid on both the rising and falling edge of the data clock.

MASTER SERIAL INTERFACE

Internal Clock

The AD7665 is configured to generate and provide the serial

data clock SCLK when the EXT/

INT pin is held low. It also

generates a SYNC signal to indicate to the host when the serial

data is valid. The serial clock SCLK and the SYNC signal can

be inverted if desired. Depending on RDC/SDIN input, the

data can be read after each conversion or during conversion.

Figure 17 and Figure 18 show the detailed timing diagrams of

these two modes.

Usually, because the AD7665 is used with a fast throughput, the

mode master, read during conversion is the most recommended

serial mode when it can be used.

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