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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD7398 датащи(PDF) 2 Page - Analog Devices |
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AD7398 датащи(HTML) 2 Page - Analog Devices |
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2 / 16 page  REV. 0 –2– AD7398/AD7399–SPECIFICATIONS AD7398 12-BIT VOLTAGE OUTPUT DAC Parameter Symbol Condition 3 V–5 V 10% 5 V 10% Unit STATIC PERFORMANCE Resolution 1 N 12 12 Bits Relative Accuracy 2 INL ±1.5 ±1.5 LSB max Differential Nonlinearity 2 DNL Monotonic ±1 ±1 LSB max Zero-Scale Error VZSE Data = 000H 7 ±2.5 mV max Full-Scale Voltage Error VFSE Data = FFFH ±2.5 ±2.5 mV max Full-Scale Tempco 3 TCVFS 1.5 1.5 ppm/ °C typ REFERENCE INPUT VREFIN Range 4 VREF 0/VDD VSS/VDD V min/max Input Resistance 5 RREF Data = 555H, Worst-Case 35 35 k Ω typ6 Input Capacitance 3 CREF 5 5 pF typ ANALOG OUTPUT Output Current IOUT Data = 800H, ∆V OUT = 4 LSB ±5 ±5 mA typ Capacitive Load 3 CL No Oscillation 200 400 pF max LOGIC INPUTS Logic Input Low Voltage VIL VDD = 3 V 0.5 V max VDD = 5 V 0.8 0.8 V max Logic Input High Voltage VIH CLK Only 80% VDD 4.0 V min 2.1–2.4 2.4 V min Input Leakage Current IIL 11 µA max Input Capacitance 3 CIL 10 10 pF max INTERFACE TIMING 3, 7 Clock Frequency fCLK 11 16.6 MHz max Clock Width High tCH 45 30 ns min Clock Width Low tCL 45 30 ns min CS to Clock Set Up tCSS 10 5 ns min Clock to CS Hold tCSH 20 15 ns min Load DAC Pulsewidth tLDAC 45 30 ns min Data Setup tDS 15 10 ns min Data Hold tDH 10 5 ns min Load Setup to CS tLDS 0 0 ns min Load Hold to CS tLDH 20 15 ns min AC CHARACTERISTICS Output Slew Rate SR Data = 000H to FFFH to 000H 22 V/ µs typ Settling Time 8 tS To ±0.1% of Full Scale 6 6 µs typ Shutdown Recovery tSDR 66 µs typ DAC Glitch Q Code 7FFH to 800H to 7FFH 150 150 nVs typ Digital Feedthrough QDF 15 15 nVs typ Feedthrough VOUT/VREF VREF = 1.5 VDC + 1 V p-p, –63 –63 dB typ Data = 000H, f = 100 kHz SUPPLY CHARACTERISTICS Shutdown Supply Current IDD_SD No Load 30/60 30/60 µA typ/max Positive Supply Current IDD VIL = 0 V, No Load 1.5/2.5 1.6/2.7 mA typ/max Negative Supply Current ISS VIL = 0 V, No Load 1.5/2.5 1.6/2.7 mA typ/max Power Dissipation PDISS VIL = 0 V, No Load 5 16 mW typ Power Supply Sensitivity PSS ∆V DD = ±5% 0.006 0.006 %/% max NOTES 1One LSB = V REF/4096 V for the 12-bit AD7398. 2The first eight codes (000 H, 007H) are excluded from the linearity error measurement in single supply operation. 3These parameters are guaranteed by design and not subject to production testing. 4When V REF is connected to either the VDD or the VSS power supply the corresponding V OUT voltage will program between ground and the supply voltage minus the offset voltage of the output buffer, which is the same as the V ZSE error specification. See additional discussion in the Operation section of the data sheet. 5Input resistance is code-dependent. 6Typicals represent average readings measured at 25 °C. 7All input control signals are specified with t R = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. 8The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground. Specifications subject to change without notice. (@ VDD = 5 V, VSS = 0 V; or VDD = +5 V, VSS = –5 V, VREF = +2.5 V, –40 C < TA < +125 C, unless otherwise noted.) |
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