AD7303

–3–

REV. 0

Parameter

Units

Conditions/Comments

33

ns min

SCLK Cycle Time

13

ns min

SCLK High Time

13

ns min

SCLK Low Time

5

ns min

SYNC

Setup Time

5

ns min

Data Setup Time

4.5

ns min

Data Hold Time

4.5

ns min

SYNC

Hold Time

33

ns min

Minimum SYNC High Time

NOTES

°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V

tr and tf should not exceed 1

µs on any input.

SCLK (I)

SYNC (I)

DIN (I)

DB15

DB0

Figure 1. Timing Diagram for Continuous 16-Bit Write

SCLK (I)

SYNC (I)

DIN (I)

DB15

DB8

DB7

DB0

Figure 2. Timing Diagram for 2

× 8-Bit Writes