AD7233

REV. A

–5–

There are two ways in which the DAC latch and hence the ana-

log output may be updated. The status of the

LDAC input is

examined after

SYNC is taken low. Depending on its status, one

of two update modes is selected.

If

LDAC = 0 then the automatic update mode is selected. In

this mode the DAC latch and analog output are updated auto-

matically when the last bit in the serial data stream is clocked in.

The update thus takes place on the sixteenth falling SCLK edge.

If

LDAC = 1 then the automatic update is disabled and the

DAC latch is updated by taking

LDAC low any time after the

16-bit data transfer is complete. The update now occurs on the

falling edge of

LDAC. This facility is useful for simultaneous

update in multi-DAC systems. Note that the

LDAC input must

be taken back high again before the next data transfer is initiated.

RESET

SCLK

–16

COUNTER/

DECODER

GATING

SIGNAL

GATED

SCLK

SDIN

INPUT SHIFT REGISTER (16 BITS)

DAC LATCH (12 BITS)

SYNC

LDAC

AUTO-UPDATE

CIRCUITRY

Figure 2. Simplified Loading Structure

SCLK

SDIN

t

4

t

3

t

5

DB15

DON'T CARE

DB0

LSB

SYNC

LDAC

DB11

MSB

DB14

DON'T CARE

DB13

DON'T CARE

DB12

DON'T CARE

t

6

t

7

t

8

DB1

Figure 3. Timing Diagram