ISL8200AMMREP datasheet(13/24 Pages) INTERSIL

13 / 24 page

ISL8200AMM

FN8287.1

November 27, 2012

Applications Information

Programming the Output Voltage (RSET)

The ISL8200AMMREP has an internal 0.6V ± 0.7% reference

voltage. Programming the output voltage requires a dividing

resistor (RSET) between the VOUT_SET pin and the VOUT

regulation point. The output voltage can be calculated as shown

in Equation 1:

Note: ISL8200AMMREP has integrated 2.2kΩ resistances into

the module dividing resistor for the bottom side (ROS). The

resistances for different output voltages in single phase

operation are listed in Table 1. For a parallel setup, please refer

to the current sharing application note (Coming Soon).

The output voltage accuracy can be improved by maintaining the

impedance at VOUTSET (internal VSEN1+) at or below 1kΩ

effective impedance. Note: the impedance between VSEN1+ and

VSEN1- is about 500kΩ.

The module has a minimum input voltage at a given output

voltage, which needs to be a minimum of 1.43 times the output

voltage if operating at FSW = 700kHz switching frequency. This is

due to the Minimum PWM OFF Time (tMIN-OFF).

The equation to determine the minimum PVIN to support the

required VOUT is given by Equations 2 and 3; it is recommended

to add 0.5V to the result to account for temperature variations.

tSW = switching period = 1/FSW

for the 700kHz switching frequency = 1428ns

For 3.3V input voltage operation, the VIN voltage is

recommended to be 5V for sufficient gate drive voltage. This can

be accomplished by using a voltage greater than or equal to 5V

on VIN, or directly connecting the 5V source to both VIN and PVCC.

VIN is the input to the internal LDO that powers the control

circuitry while PVCC is the output of the aforementioned LDO.

PVIN is the power input to the power stage. Figure 21 shows a

scenario where the power stage is running at 3.3V and the

control circuitry is running at 5.0V; keep in mind that the PVCC

pin is also at 5.0V to ensure that the LDO is not functioning.

Figure 22 shows a setup where both the control circuitry and the

power stage is at a 5.0V rail. It is imperative to not cross 5.5V in

this setup as that is the voltage limit on the PVCC pin. Figure 23

is a more general setup and can accommodate VIN ranges up to

20V; PVCC is not tied to VIN and hence the control circuitry is

The circuit shown in Figure 24 ensures proper startup by injecting

current into the ISHARE line until all phases are ready to start

regulating.

TABLE 1. VOUT - RSET

VOUT

0.6V

0.8V

1.0V

1.2V

RSET

0Ω

732Ω

1.47kΩ

2.2kΩ

VOUT

1.5V

1.8V

2.0V

2.5V

RSET

3.32kΩ

4.42kΩ

5.11kΩ

6.98kΩ

VOUT

3.3V

5.0V

6.0V

RSET

10kΩ

16.2kΩ

20kΩ

VOUT

0.6

RSET

ROS

-------------

⎝⎠

⎜⎟

⎛⎞

(EQ. 1)

PVIN_MIN

VOUT tSW

tSW tMIN_OFF

–

---------------------------------------

(EQ. 2)

PVIN_MIN

1.43 VOUT

(EQ. 3)

FIGURE 21. 3.3V OPERATION

VIN = 5.0V

VOUT

RSET

VOUT_SET

VSEN_REM-

PVIN

ISL8200AMMREP

POWER MODULE

VIN

VOUT

ISHARE

PGND1

VEN

PVCC = 5.0V

10µF

PVIN = 3.3V

VIN = 5.0V

VOUT

RSET

10µF

VOUT_SET

VSEN_REM-

PVIN

ISL8200AMMREP

POWER MODULE

VIN

VOUT

ISHARE

PGND1

VEN

PVCC = VIN

DO NOT CROSS 5.5V

FIGURE 22. 5.0V OPERATION

VIN = 5V-20V

VOUT

RSET

10µF

VOUT_SET

VSEN_REM-

PVIN

ISL8200AMMREP

POWER MODULE

VIN

VOUT

ISHARE

PGND1

VEN

FIGURE 23. 5V TO 20V OPERATION

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