AD6623PCB datasheet(12/40 Pages) AD

12 / 40 page

REV. 0

AD6623

–12–

128 PIN FUNCTION DESCRIPTIONS

Pin Number

Mnemonic

Type

Description

1, 3–5, 9, 19–21, 31, 32, 34–36, 38, 39,

42, 52–54, 64–65, 68, 72, 83–85, 95, 96,

98, 99, 102, 103, 116, 128

GND

Ground Connection

OEN

Active High Output Enable Pin

29, 28, 27, 25, 24, 23, 22, 18, 17, 16, 15,

13, 12, 11, 10, 8, 7, 6

OUT[17:0]

O/T

Parallel Output Data

47, 59, 66, 104, 127

VDD

2.5 V Supply

14, 26, 41, 78, 90, 110, 122

VDDIO

3.3 V Supply

QOUT

O/T

When HIGH indicates Q Output Data

(Complex Output Mode)

33, 37, 40, 43, 44, 45, 46, 48

D[7:0]

I/O/T

Bidirectional Microport Data

DS (RD)

INM Mode: Read Signal, MNM Mode: Data Strobe Signal

DTACK

(RDY)

Acknowledgment of a Completed Transaction (Signals when

µP Port Is Ready for an Access) Open Drain, Must Be

Pulled Up Externally

RW (

WR)

Active HIGH Read, Active Low Write

MODE

Sets Microport Mode: MODE = 1, MNM Mode; MODE = 0,

INM Mode

56, 57, 58

A[2:0]

Microport Address Bus

Chip Select, Active low enable for

µP Access

RESET2

Active Low Reset Pin

SYNC0

SYNC Signal for Synchronizing Multiple AD6623s

SYNC1

SYNC Signal for Synchronizing Multiple AD6623s

CLK

Input Clock

SYNC2

SYNC Signal for Synchronizing Multiple AD6623s

QIN

When HIGH indicates Q input data (Complex Input Mode)

71, 74–77, 79–82, 86–89, 91–94, 97

INOUT[17:0]

I/O

Wideband Input/Output Data (Allows Cascade of Multiple

AD6623 Chips In a System)

SYNC3

SYNC Signal for Synchronizing Multiple AD6623s

100

TRST2

Test Reset Pin

101

TCK

Test Clock Input

105

SDFIA

Serial Data Frame Input—Channel A

106

TMS

Test Mode Select

107

TDO

Test Data Output

108

TDI

Test Data Input

109

SCLKA

I/O

Bidirectional Serial Clock—Channel A

111

SDFOA

Serial Data Frame Sync Output—Channel A

112

SDINA

Serial Data Input—Channel A

113

SCLKB

I/O

Bidirectional Serial Clock—Channel B

114

SDFOB

Serial Data Frame Sync Output—Channel B

115

SDFIB

Serial Data Frame Input —Channel B

117

SDFIC

Serial Data Frame Input—Channel C

118

SDINB

Serial Data Input—Channel B

119

SCLKC

I/O

Bidirectional Serial Clock—Channel C

120

SDFOC

Serial Data Frame Sync Output—Channel C

121

SDINC

Serial Data Input—Channel C

123

SCLKD

I/O

Bidirectional Serial Clock—Channel D

124

SDFOD

Serial Data Frame Sync Outpu—Channel D

125

SDIND

Serial Data Input—Channel D

126

SDFID

Serial Data Frame Input—Channel D

NOTES

1Pins with a Pull-Down resistor of nominal 70 k

Ω.

2Pins with a Pull-Up resistor of nominal 70 k

Ω.

AD6623PCB датащи(PDF) 12 Page - Analog Devices

AD6623PCB датащи(HTML) 12 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

датащи скачать

ссылки URL