REV. A

AD629

–3–

ABSOLUTE MAXIMUM RATINGS

1

±18 V

DIP (N) . . . . . . . . . . . . . . . . . . . . . . . . See Derating Curves

SOIC (R) . . . . . . . . . . . . . . . . . . . . . . . See Derating Curves

Input Voltage Range, Continuous . . . . . . . . . . . . . . . .

±300 V

Common-Mode and Differential, 10 sec . . . . . . . . . . .

±500 V

Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite

Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150

°C

Operating Temperature Range . . . . . . . . . . –55

°C to +125°C

Storage Temperature Range . . . . . . . . . . . . –65

°C to +150°C

Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300

°C

NOTES

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may effect device reliability.

θ

°C/W; 8-Lead

SOIC Package,

θ

°C/W.

AMBIENT TEMPERATURE – C

2.0

–50

1.5

1.0

0.5

0

8-LEAD MINI-DIP PACKAGE

–40 –30 –20 –10

0

102030

405060

708090

8-LEAD SOIC PACKAGE

Figure 3. Derating Curve of Maximum Power Dissipation

vs. Temperature for SOIC and PDIP Packages

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD629 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

THEORY OF OPERATION

The AD629 is a unity gain differential-to-single-ended amplifier

(Diff Amp) that can reject extremely high common-mode

signals (in excess of 270 V with 15 V supplies). It consists of an

operational amplifier (Op Amp) and a resistor network.

In order to achieve high common-mode voltage range, an internal

resistor divider (Pin 3, Pin 5) attenuates the noninverting signal

by a factor of 20. Other internal resistors (Pin 1, Pin 2, and the

feedback resistor) restores the gain to provide a differential gain

of unity. The complete transfer function equals:

Laser wafer trimming provides resistor matching so that common-

mode signals are rejected while differential input signals are

amplified.

The op amp itself, in order to reduce output drift, uses super

beta transistors in its input stage The input offset current and

its associated temperature coefficient contribute no appreciable

output voltage offset or drift. This has the added benefit of

reducing voltage noise because the corner where 1/f noise becomes

dominant is below 5 Hz. In order to reduce the dependence of

gain accuracy on the op amp, the open-loop voltage gain of the

op amp exceeds 20 million, and the PSRR exceeds 140 dB.

1

2

3

4

8

7

6

5

21.1k

380k

380k

380k

20k

REF(–)

–IN

+IN

NC

OUTPUT

REF(+)

AD629

NC = NO CONNECT

Figure 4. Functional Block Diagram

ORDERING GUIDE

Temperature

Package

Package

Model

Range

Description

Option

AD629AR

–40

°C to +85°C

8-Lead Plastic SOIC

SO-8

AD629AR-REEL

1

–40

°C to +85°C

8-Lead Plastic SOIC

SO-8

AD629AR-REEL7

2

–40

°C to +85°C

8-Lead Plastic SOIC

SO-8

AD629BR

–40

°C to +85°C

8-Lead Plastic SOIC

SO-8

AD629BR-REEL

1

–40

°C to +85°C

8-Lead Plastic SOIC

SO-8

AD629BR-REEL7

2

–40

°C to +85°C

8-Lead Plastic SOIC

SO-8

AD629AN

–40

°C to +85°C

8-Lead Plastic DIP

N-8

AD629BN

–40

°C to +85°C

8-Lead Plastic DIP

N-8

NOTES