AT86RF233 datasheet(21/196 Pages) ATMEL

21 / 196 page

8351B–MCU Wireless–06/12

AT86RF233

Notes:

The SRAM access mode is not intended to be used as an alternative to the

Frame Buffer access modes (see Section 6.3.2).

Frame Buffer access violations are not indicated by a TRX_UR interrupt when

using the SRAM access mode, for further details refer to Section 9.3.3.

6.4 Radio Transceiver Status information

Each Atmel AT86RF233 SPI access can be configured to return status information of the

radio transceiver (PHY_STATUS) to the microcontroller using the first byte of the data

transferred via MISO.

The content of the radio transceiver status information can be configured using register

bits SPI_CMD_MODE (register 0x04, TRX_CTRL_1). After reset, the content on the

first byte send on MISO to the microcontroller is set to zero.

6.4.1 Register Description

Note:

Throughout this datasheet, underlined values indicate reset settings.

The TRX_CTRL_1 register is a multi-purpose register to control various operating

modes and settings of the radio transceiver.

Figure 6-15. Register TRX_CTRL_1.

Bit

0x04

PA_EXT_EN

IRQ_2_EXT_EN

TX_AUTO_CRC_

RX_BL_CTRL

TRX_CTRL_1

Read/Write

R/W

Reset value

Bit

0x04

SPI_CMD_MODE

IRQ_MASK_MODE

IRQ_POLARITY

TRX_CTRL_1

Read/Write

R/W

Reset value

 Bit 3:2 - SPI_CMD_MODE

Each SPI transfer returns bytes back to the SPI master. The content of the first byte

(PHY_STATUS) can be configured using register bits SPI_CMD_MODE.

Table 6-4. SPI_CMD_MODE.

Value

Description

SPI_CMD_MODE

Default (empty, all bits zero)

Monitor TRX_STATUS register

Monitor PHY_RSSI register

Monitor IRQ_STATUS register

Note:

More information to register TRX_STATUS, see Section 7.1.5, to register

PHY_RSSI, see Section 8.3, and to register IRQ_STATUS, see Section 6.7.

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