AD604ARS datasheet(15/20 Pages) AD

15 / 20 page

AD604

REV. 0

–15–

This dc voltage will now be forced equal to the voltage, VSET, by

the control loop. The squarer together with the low-pass filter

functions as a mean-square detector. As should be evident, by

controlling the value of VSET, we can set the amplitude of the

voltage V1 at the input of the AD835; if VSET equals minus

80 mV, the AGC output signal amplitude will be

±400 mV.

Figure 45 shows the control voltage, VGN, versus the input

power at frequencies of 1 MHz (solid line) and 10 MHz (dashed

line) at an output regulated level of +2 dBm (800 mV p-p). The

AGC threshold is evident at a PIN of about –79 dBm; the high-

est input power that could still be accommodated was about

+3 dBm. At this level the output starts being distorted because

of clipping in the preamplifier.

PIN – dBm

4.5

4.0

0.5

–40

3.5

3.0

1.0

2.5

2.0

1.5

–80

–70

–60

–50

–30

–20

–10

1MHz

10MHz

Figure 45. Control Voltage vs. Input Power of Circuit in

Figure 42

As mentioned already, the second preamplifier can be used to

extend the range of the AGC circuit in Figure 42. Figure 46

shows the modifications that need to be made to Figure 44 to

achieve 96 dB of gain and dynamic range. Because of the ex-

tremely high gain, the bandwidth needs to be limited to reject

some of the noise; furthermore, limiting the bandwidth will help

suppress high frequency oscillations. The added components act

as a low-pass filter and dc block (C5 level shifts the output of

the first DSX from 2.5 V to ground); the ferrite bead has an im-

pedance of about 5

Ω at 1 MHz, 30 Ω at 10 MHz, and 70 Ω at

100 MHz. Together with R2 and C6, the bead makes a low-pass

filter which attenuates higher frequencies; at 1 MHz the attenu-

ation is about –0.2 dB, while at 10 MHz it increases to –6 dB, on

to –28 dB at 100 MHz. Signals now have to be less than about

1 MHz to not be significantly affected by the added circuitry.

In Figure 47 we see the control voltage vs. input power at

1 MHz to the circuit in Figure 46; note that the AGC threshold

is at –95 dBm. The output signal level was set to 800 mV p-p by

applying –80 mV to the VSET connector.

AD604

0.1µF

499

Ω

560pF

0.1µF

FAIR-RITE

#2643000301

–DSX1

+DSX1

PAI1

FBK1

PAO1

COM1

COM2

PAI2

FBK2

PAO2

+DSX2

–DSX2

VGN1

VREF

VPOS

GND1

OUT1

VNEG

VPOS

GND2

OUT2

VOCM

VGN2

Figure 46. Modifications of AGC Amplifier to Get 96 dB of

Gain Range

PIN – dBm

4.5

4.0

–100

–40

3.5

3.0

1.0

2.5

2.0

1.5

–90

–80

–70

–60

–50

–30

–20

–10

1MHz

0.5

Figure 47. Control Voltage vs. Input Power of Circuit in

Figure 46

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