Product Specifications

PART NO.:

VL470L2925-B3SG

REV: 1.0

Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA –

www.virtium.com

7

AC TIMING PARAMETERS & SPECIFICATIONS

Parameter

Symbol

CC

(DDR400)

B3

(DDR333)

B0

(DDR266)

Unit

Min

Max

Min

Max

Min

Max

Row cycle time

tRC

55

60

65

ns

Refresh row cycle time

tRFC

70

72

75

ns

Row active time

tRAS

40

70K

42

70K

45

120K

ns

RAS to CAS delay

tRCD

15

18

20

ns

Row precharge time

tRP

15

18

20

ns

Row active to Row active delay

tRRD

10

12

15

ns

Write recovery time

tWR

15

15

15

ns

Last data in to Read command

tWTR

2

1

1

tCK

Clock cycle time

CL=2.0

tCK

-

-

7.5

12

10

12

ns

CL=2.5

6

12

6

12

7.5

12

CL=3.0

5

10

-

-

-

-

Clock high level width

tCH

0.45

0.55

0.45

0.55

0.45

0.55

tCK

Clock low level width

tCL

0.45

0.55

0.45

0.55

0.45

0.55

tCK

DQS-out access time from CK/CK

tDQSCK

-0.55

+0.55

-0.6

+0.6

-0.75

+0.75

ns

Output data access time from CK/CK

tAC

-0.65

+0.65

-0.7

+0.7

-0.75

+0.75

ns

Data strobe edge to ouput data edge

tDQSQ

-

0.4

-

0.4

-

0.5

ns

Read Preamble

tRPRE

0.9

1.1

0.9

1.1

0.9

1.1

tCK

Read Postamble

tRPST

0.4

0.6

0.4

0.6

0.4

0.6

tCK

CK to valid DQS-in

tDQSS

0.72

1.28

0.75

1.25

0.75

1.25

tCK

DQS-in setup time

tWPRES

0

0

0

ns

DQS-in hold time

tWPRE

0.25

0.25

0.25

tCK

DQS falling edge to CK rising-setup time

tDSS

0.2

0.2

0.2

tCK

DQS falling edge from CK rising-hold time

tDSH

0.2

0.2

0.2

tCK

DQS-in high level width

tDQSH

0.35

0.35

0.35

tCK

DQS-in low level width

tDQSL

0.35

0.35

0.35

tCK

Address and Control Input setup time(fast)

tIS

0.6

0.75

0.9

ns

Address and Control Input hold time(fast)

tIH

0.6

0.75

0.9

ns

Address and Control Input setup time(slow)

tIS

0.7

0.8

1.0

ns

Address and Control Input hold time(slow)

tIH

0.7

0.8

1.0

ns

Data-out high impedence time from CK/CK

tHZ

-0.65

+0.65

-0.7

+0.7

-0.75

+0.75

ns

Data-out low impedence time from CK/CK

tLZ

-0.65

+0.65

-0.7

+0.7

-0.75

+0.75

ns

Mode register set cycle time

tMRD

10

12

15

ns

DQ & DM setup time to DQS

tDS

0.4

0.45

0.5

ns

DQ & DM hold time to DQS

tDH

0.4

0.45

0.5

ns

Control & Address input pulse width

tIPW

2.2

2.2

2.2

ns

DQ & DM input pulse width

tDIPW

1.75

1.75

1.75

ns

Exit self refresh to non-Read command

tXSNR

75

75

75

ns

Exit self refresh to read command

tXSRD

200

200

200

tCK

Refresh interval time

tREFI

7.8

7.8

7.8

us

Output DQS valid window

tQH

tHP

-tQHS

-

tHP

-tQHS

-

tHP

-tQHS

-

ns

Clock half period

tHP

tCLmin

or tCHmin

-

tCLmin

or tCHmin

-

tCLmin

or tCHmin

-

ns

Data hold skew factor

tQHS

0.5

0.55

0.75

ns

DQS write postamble time

tWPST

0.4

0.6

0.4

0.6

0.4

0.6

tCK

Active to Read with Auto precharge

command

tRAP

15

18

20

Autoprecharge write recovery + Precharge

time

tDAL

(tWR/tCK)

+

(tRP/tCK)

(tWR/tCK)

+

(tRP/tCK)

(tWR/tCK)

+

(tRP/tCK)

tCK

Power Down Exit Time

tPDEX

1

1

1

tCK