AD5583 datasheet(2/8 Pages) AD

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PRELIMINARY TECHNICAL DATA

AD5582/AD5583

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future

manufacture unless otherwise agreed to in writing.

REV PrC, 23 APR '01

ELECTRICAL CHARACTERISTICS at VDD =+5V, VSS = -5V, VL = +5V±10%, VREFH = +2.5V, VREFL = -2.5V, -40°C < TA < +125°C, unless otherwise noted.

PARAMETER

SYMBOL

CONDITION

MIN

TYP

MAX

UNITS

STATIC PERFORMANCE

Resolution

AD5582

Bits

Resolution

AD5583

Bits

Relative Accuracy

INL

-1

LSB

Differential Nonlinearity

DNL

Monotonic

-1

LSB

Zero-Scale Error

VZSE

Data = 000H

LSB

Full-Scale Voltage Error

VFSE

Data = FFFH

LSB

Full-Scale Tempco

TCVFS

ppm/

REFERENCE INPUT

VREFH Input Range

VREFH

VSS

VREFL Input Range

VREFL

VSS

Input Resistance

RREF

Data = 555H

Ω5

Input Capacitance

CREF

REF Input Current

IREF

500

µA

REF Multiplying Bandwidth

BWREF

ANALOG OUTPUT

Output Current

IOUT

Data = 800H, ∆VOUT = 4LSB

±2

Capacitive Load

No Oscillation

500

LOGIC INPUTS

Logic Input Low Voltage

VIL

VL = 5V ± 10%

0.8

Logic Input High Voltage

VIH

VL = 5V ± 10%

2.4

Input Leakage Current

IIL

µA

Input Capacitance

CIL

Output Voltage High

VOH

IOH = -0.8mA

2.4

Output Voltage Low

VOL

IOL = 1.6mA

0.4

AC CHARACTERISTICS

Output Slew Rate

Data = 000H to FFFH to 000H

µs

Settling Time

To ±0.1% of Full Scale

µs

Shutdown Recovery

tSDR

µs

DAC Glitch

Code 7FFH to 800H to 7FFH

100

nVs

Digital Feed Through

VOUT/tCS

Data=800H, CS toggles at f=16MHz

nVs

Analog Crosstalk

VOUT/VREF

VREF = 1.5VDC +1VP-P, Data = 000H, f=100KHz

-80

Output Noise

√Hz

SUPPLY CHARACTERISTICS

Positive Supply Current

IDD

VIL = 0V, No Load

Negative Supply Current

ISS

VIL = 0V, No Load

Power Dissipation

PDISS

VIL = 0V, No Load

Power Supply Sensitivity

PSS

∆VDD = ±5%

ppm/V

NOTES:

DAC Output Equation: VOUT = VREFL + [(VREFH-VREFL)*Code/2^N], where Code = data loaded in corresponding DAC register A, B, C, D and N equals the

DAC resolution AD5582 = 12, AD5583 = 10 bits. One LSB = VREF/4096V for the 12-bit AD5582.

The first two codes (000H, 001H) are excluded from the linearity error measurement in single supply operation.

These parameters are guaranteed by design and not subject to production testing.

When VREF is connected to either the VDD or the VSS power supply the corresponding VOUT voltage will program between ground and the supply voltage

minus the offset voltage of the output buffer, which is the same as the VZSE error specification. See additional discussion in the operation section of the data

sheet.

Typical specifications represent average readings measured at 25°C.

The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground in single supply operation.

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