AD5544ARS datasheet(15/16 Pages) AD

15 / 16 page

REV. 0

AD5544/AD5554

–15–

SHIFT REGISTER

ADDRESS

DECODER

TO INPUT REGISTER

19TH/17TH

CLOCK

SDO

SDI

CLK

Figure 9. AD5544/AD5554 Equivalent Logic Interface

POWER-ON RESET

When the VDD power supply is turned ON, an internal reset

strobe forces all the Input and DAC registers to the zero-code

state or half-scale, depending on the MSB pin voltage. The VDD

power supply should have a smooth positive ramp without

drooping in order to have consistent results, especially in the

region of VDD = 1.5 V to 2.3 V. The VSS supply has no effect on

the power-ON reset performance. The DAC register data will

stay at zero or half-scale setting until a valid serial register data

load takes place.

ESD Protection Circuits

All logic-input pins contain back-biased ESD protection Zeners

connected to ground (DGND) and VDD as shown in Figure 9.

VDD

DIGITAL

INPUTS

DGND

Figure 10. Equivalent ESD Protection Circuits

PCB LAYOUT

In PCB layout, all analog ground, AGNDX, should be tied together.

Ampliﬁers suitable for I-to-V conversion include:

• High Accuracy: OP97, OP297

• Speed and Accuracy: OP42

•

±5 V Applications: OP162/OP262/OP462, OP184/OP284/

OP484

APPLICATIONS

The AD5544/AD5554 are inherently 2-quadrant multiplying

D/A converters. That is, they can be easily set up for unipolar

output operation. The full-scale output polarity is the inverse of

the reference-input voltage.

In some applications it may be necessary to generate the full 4-

quadrant multiplying capability or a bipolar output swing. This

is easily accomplished using an additional external ampliﬁer

(A2) conﬁgured as a summing ampliﬁer (see Figure 11). In this

circuit the ﬁrst and second ampliﬁers (A1 and A2) provide a

total gain-of-2 which increases the output voltage span to 20 V.

Biasing the external ampliﬁer with a 10 V offset from the refer-

ence voltage results in a full 4-quadrant multiplying circuit. The

transfer equation of this circuit shows that both negative and

positive output voltages are created as the input data (D) is

incremented from code zero (VOUT = –10 V) to midscale (VOUT

= 0 V) to full-scale (VOUT = 10 V).

OUT

REF

=−









32768

(For AD5544)

(Equation 3)

OUT

REF

=−









8192

(For AD5554)

(Equation 4)

ONE CHANNEL

AD5544

IOUTX

RFBX

VREFX

VDD

VSS

AGNDFAGNDX

VOUT

10k

AD588

VREF

10V

DIGITAL INTERFACE CONNECTIONS

OMITTED FOR CLARITY.

–10V < VOUT < +10V

Figure 11. Four-Quadrant Multiplying Application Circuit

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