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AD9525BCPZ датащи(PDF) 44 Page - Analog Devices

номер детали AD9525BCPZ
подробное описание детали  Low Jitter Clock Generator with Eight LVPECL Outputs
PDF  48 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD9525BCPZ датащи(HTML) 44 Page - Analog Devices

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AD9525
Data Sheet
Rev. 0 | Page 44 of 48
Table 48. VCO, Reference, and CLK Inputs
Reg.
Addr.
(Hex)
Bits
Bit Name
Description
0x1E0
[7:3]
Don’t care
Don’t care.
[2:0]
M divider
M divider value.
Bit 2
Bit 1
Bit 0
Divider Value
0
0
0
1
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
1
0
1
6
1
1
0
7
1
1
1
8
Table 49. Other
Reg.
Addr.
(Hex)
Bits
Name
Description
0x230
[7:5]
Don’t care
Don’t care.
4
Dist all power-down
Powers down all of distribution. Puts all drivers in safe power-down mode.
0 (default): enabled.
1: power-down.
3
CLKIN power-down
Powers down CLKIN, CLKIN.
0 (default): enabled.
1: power-down.
2
M divider power-down
Powers down M divider.
0 (default): enabled.
1: power-down.
1
Distribution reference
power-down
Power down distribution reference. This bit should be asserted only when the drivers do not
need the safe power-down mode guidelines.
0 (default): enabled.
1: power-down.
0
PLL power-down
Power down PLL.
0 (default): enabled.
1: power-down.
232
[7:1]
Don’t care
Don’t care.
0
IO_UPDATE
This bit must be set to 1b to transfer the contents of the buffer registers into the active registers.
This happens on the next SCLK rising edge. This bit is self-clearing; that is, it does not have to be
set back to 0.
1 (self-clearing): update all active registers to the contents of the buffer registers.



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