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AD5231 датащи(PDF) 14 Page - Analog Devices |
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AD5231 датащи(HTML) 14 Page - Analog Devices |
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14 / 20 page ![]() REV. 0 –14– AD5232 Table X. Active Trimming of One POT Followed by a Save to Nonvolatile Memory (PCB Calibrate) SDI SDO Action B040H XXXXH Loads 40H data into RDAC1 register, Wiper W1 moves to 1/4 full-scale position. E0XXH B040H Increments RDAC1 register by one to 41H, Wiper W1 moves one resistor segment away from terminal B. E0XXH E0XXH Increments RDAC1 register by one to 42H, Wiper W1 moves one more resistor segment away from terminal B. Continue until desired wiper position reached. 20XXH E0XXH Saves RDAC1 register data into corresponding nonvolatile EEMEM1 memory ADDR = 0H. EQUIPMENT CUSTOMER STARTUP SEQUENCE FOR A PCB CALIBRATED UNIT WITH PROTECTED SETTINGS PCB setting: Tie WP to GND [prevents changes in PCB wiper set position] Power VDD and VSS with respect to GND Optional: Strobe PR pin [ensures full power ON preset of wiper register with EEMEM contents in unpredictable supply sequencing environments] Table XI. Using Left Shift by One to Change Circuit Gain in 6 dB Steps SDI SDO Action C1XXH XXXXH Moves Wiper W2 to double the present data value contained in RDAC2 regis- ter, in the direction of the A terminal. C1XXH XXXXH Moves Wiper W2 to double the present data value contained in RDAC2 regis- ter, in the direction of the A terminal. Table XII. Storing Additional Data in Nonvolatile Memory SDI SDO Action 3280H XXXXH Stores 80H data into spare EEMEM location USER1. 3340H XXXXH Stores 40H data into spare EEMEM location USER2. Table XIII. Reading Back Data from Various Memory Locations SDI SDO Action 94XXH XXXXH Prepares data read from USER3 location. Assumption: USER3 previously loaded with 80H. 00XXH XX80H NOP instruction #0 sends 16-bit word out of SDO where the last 8 bits con- tain the contents of USER3 location. NOP command ensures device returns to idle power dissipation state. Analog Devices offers the AD5232EVAL board for sale to simplify evaluation of these programmable devices controlled by a personal computer via the printer port. TEST CIRCUITS Figures 13 to 22 define the test conditions used in the product specification’s table. A W B NC IW DUT VMS NC = NO CONNECT Figure 13. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) A W B DUT VMS V+ V+ = V DD 1LSB = V+/2N Figure 14. Potentiometer Divider Nonlinearity Error Test Circuit (INL, DNL) A W B DUT IW VMS1 VMS2 VW RW = [VMS1 – V MS2]/IW Figure 15. Wiper Resistance Test Circuit A W B VMS V+ = V DD 10% PSRR (dB) = 20 LOG VMS VDD ( ) ~ VA VDD VMS% VDD% PSS (%/%) = V+ Figure 16. Power Supply Sensitivity Test Circuit (PSS, PSRR) ~ OFFSET BIAS OFFSET GND AB DUT W 5V VIN VOUT OP279 Figure 17. Inverting Gain Test Circuit |
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